International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395 -0056
Volume: 04 Issue: 07 | July -2017
p-ISSN: 2395-0072
www.irjet.net
Design and Implementation of Wallace Compressor Multiplier using Vedic Mathematics Pooja R. Sarangpure1, Devendra S. Chaudhari2, Yogita D. Kapse3 1M.Tech
student, Electronics and Telecommunication, Government College of Engineering, Jalgaon, Maharashtra, India 2Professor, Electronics and Telecommunication, Government College of Engineering, Jalgaon, Maharashtra, India 3 Assistant professor, Electronics and Telecommunication, Government College of Engineering, Jalgaon, Maharashtra, India ---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract -For arithmetic multiplication various Vedic
not a good approach as it involves several time consuming operations.
multiplication techniques like Urdhvatiryakbhyam, Nikhilam and Anurupye have been used. It has been found that Urdhvatiryakbhyam Sutra is the most suitable which gives minimum delay for multiplication of all types of numbers. With the advent of new technology in the domain of VLSI, communication and signal processing, there is an ever growing demand for the high speed processing and low area design. In this paper, a modified compressor based multiplier is introduced that is 4:2 compressor and the Wallace compressor architectures. In addition to that it uses Vedic mathematics to get a high speed multiplication operation. In various applications of digital signal processing, multiplication is one of the key components. Vedic technique removes the redundant multiplication steps thus it reduce the propagation delay in processor and hence it reduce the hardware complexity in terms of area and memory requirement. This Vedic multiplier was coded in VHDL by using Xilinx ISE 13.2. The synthesis results indicated that the computation time delay for 4:2 compressor multipliers was 15.83ns and 12.71ns for Wallace compressor Vedic Multiplier.
1.1Digital Logic Design A digital computer stores data in terms of digits (numbers) and proceeds in discrete steps from one state to the next state. The states of a digital computer typically involve bits. Digital logic is the basis of any electronic systems, such as computers and cell phones. Digital logic is rooted in binary code, a series of zeroes and ones each having an opposite value. This system facilitates the design of electronic circuits that convey information, including logic gates. Digital logic gate functions include and, or and not. The value system translates input signals into specific output. Digital logic facilitates computing, robotics and other electronic applications. The advent of integrated circuit technology has made it easier to design digital circuits. Today, the designer is not required to know the basic operation of various components such as capacitors, transistors etc. This involves complex mathematical calculations. For a given set of inputs the digital circuit always produces the same output at any instant of time unlike analog circuits whose outputs vary with variation. Digital signals are more robust and simple than analog signals with respect to temperature and process variations.
Key Words: multiplier, 4:2 compressors, Wallace compressor, Xilinx 13.2, etc.
1. INTRODUCTION
1.2 Vedic Multiplier
The processor speed depends on its multiplier’s performance. This in turn raises the demand for multipliers for which operate with high speed as well as maintain low area and moderate power dissipation. Over the past few decades, several new novel architectures have been introduced, designed and explored. Booth’s and modified Booth’s algorithm based multipliers are quite popular in having modern VLSI design with some short comes. In these multiplier algorithms, the multiplication process, involves several transitional step before arriving at the final value. The intermediate stages include several additions, subtractions and comparisons which reduce the speed exponentially with the total number of bits present in the multiplier and the multiplicand. Since the speed is the major concern in any system, utilizing such type of architectures is
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The Sanskrit word “Veda” is derived from the word “Vid”, meaning to know without limit. The word “Veda” covers all veda-sakhas known to the humanity. Figure 1 shows basic block diagram of multiplier. The input signal is step by step compressed and multiplication operations perform to obtain the result. Input
Output Compressor
Multiplier
Fig -1: Basic Block Diagram of a Multiplier A mathematician, Sri Bharati Krishna Tirthaji rediscovered Vedic mathematics that being there during
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