International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 12 Issue: 05 | May 2025
p-ISSN: 2395-0072
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Design of a Custom RISC-V SoC Optimized for Neuromorphic Edge AI Workloads Abin Babu1, Anil M2 1M.Tech Embedded system ,Vidya Academy of Science and Technology, Thrissur
2Assistant Professor, Dept. Electronics and Communication Engineering, Vidya Academy of Science and
Technology, Thrissur, kerala, India ---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract -This paper presents the design of a custom
Additionally, the SoC features a reconfigurable interconnect fabric, allowing seamless integration with various sensor types, such as vision and audio sensors, which are common in edge AI systems. A Dynamic Voltage and Frequency Scaling (DVFS) controller is incorporated to further optimize power consumption, ensuring that the SoC operates efficiently in always-on systems. By leveraging the open-source RISC-V ecosystem, this design offers a highly customizable solution that enables the development of next-generation edge AI devices, capable of real-time learning and decision-making in a low-power, cost-effective manner.
RISC-V-based System-on-Chip (SoC) tailored for neuromorphic computing at the edge, targeting ultra-lowpower AI applications. The proposed architecture integrates a lightweight Spiking Neural Network (SNN) accelerator that is tightly coupled with a RISC-V core to enable efficient, event-driven processing. To support adaptability across various AI workloads and sensor modalities, a reconfigurable interconnect fabric is introduced, allowing seamless integration with devices such as event-based cameras, microphones, and inertial sensors. In addition, the design features a Dynamic Voltage and Frequency Scaling (DVFS) controller that intelligently adjusts power consumption based on computational demand, making it suitable for always-on applications. By leveraging the flexibility of the open-source RISC-V ecosystem, this SoC offers a customizable, energy-efficient solution for real-time edge AI tasks such as vision processing, audio recognition, and human activity detection. The proposed system demonstrates significant potential for use in wearables, smart environments, and battery-constrained embedded systems.
1.1 System Architecture The proposed System-on-Chip (SoC) architecture is built around a modular RISC-V core, designed for neuromorphic edge computing tasks. At the heart of the system lies a lightweight Spiking Neural Network (SNN) accelerator that is tightly coupled with the RISC-V processor. This integration enables efficient event-driven processing, which is essential for real-time AI tasks such as gesture recognition and audio pattern detection. The SNN accelerator is optimized to handle sparse and temporal data, reducing computational load and power consumption.
Key Words: Edge AI, Neuromorphic Computing, RISCV, Spiking Neural Network, DVFS, Wearable Systems
1.INTRODUCTION
To accommodate diverse sensors and workload requirements, the SoC includes a reconfigurable interconnect fabric. This fabric facilitates flexible interfacing with event-based vision sensors, microphones, and inertial measurement units (IMUs). It also supports runtime adaptation to different neural network topologies and data paths.
Neuromorphic computing, which draws inspiration from the architecture and function of biological neural systems, offers a promising approach to address the increasing demand for energy-efficient and real-time AI processing. Traditional AI systems, while powerful, struggle with the inherent limitations of power consumption and latency, particularly in edge devices such as wearables, surveillance systems, and IoT devices. These devices require processing capabilities that are both highly efficient and capable of continuous, real-time learning in dynamic environments.
A dedicated Dynamic Voltage and Frequency Scaling (DVFS) controller monitors workload activity and system requirements, adjusting voltage and clock frequencies dynamically. This ensures minimal energy usage in idle states and adequate performance during computational peaks. The entire system is synthesized using industrystandard EDA tools, with emphasis on minimizing area and energy.
In this paper, we present a custom RISC-V-based Systemon-Chip (SoC) designed specifically for neuromorphic computing in edge AI applications. The architecture integrates a lightweight Spiking Neural Network (SNN) accelerator, tightly coupled with the RISC-V core, to perform event-driven computations efficiently.
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