International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 04 Issue: 07 | July -2017
p-ISSN: 2395-0072
www.irjet.net
UNIVERSAL VERIFICATION METHODOLOGY BASED VERIFICATION ENVIRONMENT FOR PCIE DATA LINK LAYER Dr.T.C.Thanuja[1] , Akshata[2] Professor, Dept. of VLSI Design & Embedded systems, VTU, Belagavi, Karnataka, India [1] PG Student, Dept. of VLSI Design & Embedded systems, VTU, Belagavi, Karnataka, India [2] ---------------------------------------------------------------------***------------------------------------------------------------------specifications are used and which are introduced by PCI Abstract— In today’s industry design complexity increased with the number of transistors hence enhance the verification complexity. Chip designer need to spend 70% of design time and size of code get reduces so efforts for verification .Peripheral component interconnect express data link layer is serial, I/O interconnect and high speed communication protocol. PCIE is layered and packets based transition protocol. Generation of different packets, flow control initialization, retry mechanisms and LCRC error check and data integrity are some of properties of Data Link Layer [DLL]. In this paper main aim is verification of all properties of data link layer using UVM And achieving the coverage goals. All these properties of DLL are verified with the aid of universal verification methodology and using Questa sim tool. The performance of verification is enhancing using modularity, reusability, and overriding mechanisms.UVM code is written by using UVM 1.1source object.
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Keywords—PCIE (Peripheral component Interconnect Express), UVM (Universal verification Method), Retry Mechanism, Questasim.
Slow devices will increases wait-states which will reduces the efficiency of bus cycles. PCI bus cycles do not indicate the transfer size. This makes buffer management within master and target devices inefficient .Delayed transactions on PCI are handled inefficiently. When a master is retried, it guesses when to try again PCI interrupt than dling architecture is in efficient specially because multiple devices share a PCI interrupt signal. Additional software latency is incurred when software discovers which device /devices that share an interrupt signal actually generated the interrupt.
1. INTRODUCTION Recently manufactured systems on chip designs are highly complex and expensive for verification of each design. At present verification engineers are using simulation based method for verification. The main challenges in verification are to verifying the design without losing the properties of coverage circuit should verified on time to market with less cost. There are many verification methods such as functional verification, assertion based verification, Formal verification. The main topic of focus is the functional verification of PCI Express protocol using universal verification methodology. PCI Express is point to point, serial protocol, high speed bus, and a switch based topology is used for transaction. Data is transferred in terms of packet. There are three layers in. Transaction layer, data link layer and physical layer. These layers are
similar to that of OSI model layers and all services are merged into three layers instead of seven layers. In this paper mainly focusing on data link layer services and verification of it. For verification of data link layer three interfaces needed to create, so that writing universal verification component for each interface. Each UVC has a monitor, test, environment, sequence, driver etc. PCIE 3.0 © 2017, IRJET
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Impact Factor value: 5.181
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2. OVERVIEW OF PCIE The PCI bus clock has a frequency of 33MHz and the address bus width is 32-bits (4GB memory address space), although PCI optionally supports64-bit address bus. The data bus width is implemented as either 32-bits or 64-bits depending on bus performance requirement. The address and data bus signals are multiplexed on the same pins (AD bus) to reduce pin count .PCI is introduced by INTEL,PCI– SIG in1993.The maximum frequency achievable with the PCI architecture is 66 MHz this is a result of the static clock method of driving and latching signals. PCI bus efficiency is in the order of 50% to 60%.The PCI specification all own master and target devices to insert wait-states during data phases of a bus cycle.
The processor's NMI interrupt input is asserted when a PCI parity or system is detected. PCI-X is a high performance evolution of conventional PCI. It uses the same hardware structure, which makes it possible to operate a PCI-X add-in card in a Conventional PCI slot, and vice-versa. The PCI-X technology is dedicated to server applications, and is therefore found on many high-end PC motherboards. PCI-X allows for a considerably higher bandwidth than conventional PCI. It is characterized by a higher clock speed (up to 133 MHz), and is usually found in the 64-bit bus width, although the 32-bit width can exist. Revision 1.0, initially issued in July 2000, specifies PCI-X as an addendum to Conventional PCI. Revision 2.0, an improvement to PCI-X specification, published in November 2002, extends the clocking capability to 266 and 533 MHz. Though PCI-X still suffers from the problem of shared bus topology and more sensitive it becomes to ISO 9001:2008 Certified Journal
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