International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395 -0056
Volume: 04 Issue: 05 | May -2017
p-ISSN: 2395-0072
www.irjet.net
Verification of Universal Memory Controller Sharada Pattar1, Mrs. Rashmi S Bhaskar2 1 Student,
Department of Electronics & Communication Engineering B.N.M.I.T. College of Engineering, Bangalore560 070, Karnataka, India 2 Assistant Professor, Department of Electronics & Communication Engineering B.N.M.I.T. College of Engineering, Bangalore-560 070, Karnataka, India ---------------------------------------------------------------------***---------------------------------------------------------------------
matching then UMC is working properly and hence verification is done
Abstract - This paper describing verification of the
Universal Memory Controller (UMC) which is compatible with WISHBONE verification IP .It involves creating a test bench for UMC as DUT. By generating a test cases the UMC features are verified and thus DUT is verified. For the verification of UMC three test cases are used .First test case involving SDRAM, second test case of SSRAM and last test case is of SYNC (synchronous chip select device).
The WISHBONE is a portable IP core .It is used in semiconductor IP for flexible design methodology WISHBONE is reusable, portable and reliable for the system. Memory modules containing a different types of memory like SDRAM, SSRAM, and SYNC. These memories attached to the UMC through memory interface. All these memory designs are written in Verilog code, these Verilog codes are included in the top file of the system Verilog module. While verification system Verilog top modules are used.
Key Words: UMC, DUT, WISHBONE, SDRAM, SSRAM, SYNC
1. INTRODUCTION
UMC is having its own architecture design with novel feature supporting. UMC is placed between WISHBONE and memory module. These blocks are interfaced by WISHBONE interface and memory interface to the UMC.
For SOC having different types of memories like SDRAM, DRAM, SSRAM, FLASH etc.., it will require different types of memory controllers for each memory types. Which will add extra space on SOC. Universal memory controller design, improved by integration of the existing memory controller in addition of providing novel features. This make the low power consumption for the design. UMC controller design which is supporting SDRM, SSRAM and SYNC memories what we call as Universal Memory Controller. This UMC design is having some specific function like, it has 8 chip select line and it support different types of memory. Single memory controller which is supporting different memories, for this UMC design, verification is done by generating a test cases in system Verilog language.
1.2 verification of UMC Verification of UMC is responsible for verification of UMC subsystem design, micro-architecture and golden models using advanced verification methodology. It executes test/coverage plans and correctness of the design is verified by working with architecture, designers. In verification for test bench, inputs are given to the design and outputs are monitored. Challenge in verification is to determine what to supply as input pattern to the design and what will be the expected output for properly working design under test.
1.1 Universal Memory Controller
Fig -2:Testbench
2. Verification Environment for UMC .
For verification of any design, verification environment has been created. Environment containing a generator (gen), bus function module (BFM), monitor, reference module, coverage, checker and scoreboard.
Fig -1: Over view of UMC Diagram explaining the general module of UMC, which is having WISHBONE block, memory controller and memory module blocks which all are interfaced each other. Wish bone block is a place where we are verifying the UMC by checking read and write dada matching, if both read and write data
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