International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395 -0056
Volume: 04 Issue: 04 | Apr -2017
p-ISSN: 2395-0072
www.irjet.net
Implementation of an Efficient Multiplier based on Vedic Mathematics Kedar N. Palata1, Vinobha K. Nadar 2, Jatin S. Jethawa 3, Tushar J. Surwadkar4 , Rajan S. Deshmukh5 1234Department
5Department
of Electronics, Rizvi College of Engineering, Maharashtra, India of Electronics and Telecommunication, Rizvi College of Engineering, Maharashtra, India
---------------------------------------------------------------------***--------------------------------------------------------------------Abstract - A High speed processor depends mostly on In this paper after the introduction of Urdhava Tiryakbhyam Sutra, Multiplier architecture is the multiplier as it one of the key hardware blocks in discussed and is illustrated with two 4 bit numbers. most digital processing system. This paper depicts and The multiplier and the multiplicand each are proposes the design of 8*8 bit binary arithmetic proposed as 4 bit numbers so that it decomposes into multiplier by using Vedic Mathematics .Vedic 4*4 multiplication module. After decomposition, mathematics is the name given to the ancient system vertical crosswise is applied to carry out the of mathematics which is rediscovered from the Vedas. multiplication on first 4*4 multiplication module. It is based on Vertical and Crosswise structure of Vedic Sutras are applied to binary multipliers using ancient Indian Vedic Mathematics. The Vedic carry save address. The Vedic Multiplier which is Mathematics also known as Urdhva Tiryagbhyam discussed in the paper performs partial product Sutra is for generating the partial product. The partial Multiplication and addition in parallel which gives a product addition in Vedic Multiplier is realized using better performance in terms of area and speed. carry-skip technique. The propound architecture is for 2. URDHVA TIRYAKBHYAM SUTRA two 4 bit numbers, the multiplier and the multiplicand In Urdhva Tiryakbhyam Sutra, Operations are which are grouped as 4 bit number, so that it performed in invertical and crosswise manner. decomposes 4*4 multiplication modules. This Multiplication operation is done by simple addition algorithms are executed in VHDL language by using of partial products. In this Sutra the parallelism Modelsim and synthesis is done in ISE Project architecture is used which means generation of Navigator Xilinx Software. partial products and their summing is performed simultaneously. Key Words: Vedic Mathematics, Urdhva Tiryagbhyam, Modelsim, ISE Project Navigator Xilinx Software, VHDL. 1. INTRODUCTION With the encroachment of VLSI technology the use for portable and DSP systems has increased efficiently . Multipliers are key components of many high performance systems such as Microprocessors ,Digital signal processors etc. The speed of the Multipliers mainly depends on the number of partial products. And also the speed of adder which are used in it. After eight years of research on ‘Vedas’, Shri Bharti Krishna Tirthaji reconstructed the Vedic Maths. According to him, Vedic Mathematics is mainly focused on sixteen very important principles or formulae which is termed as Sutras. The variety of applications of vedic mathematics includes Compound Multiplications, Algebraic Operations, Squaring, Cubing, Cuberoot, Quadratic Equation and Co-ordinate Geometry. © 2017, IRJET
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Fig.1: Multiplication of two decimal numbers by Urdhva ISO 9001:2008 Certified Journal
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