International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395 -0056
Volume: 04 Issue: 04 | Apr -2017
p-ISSN: 2395-0072
www.irjet.net
Design of Complex Multiplier for FFT implementation using Vedic Mathematics Ramya Devi.K1, Revathy.R2, Sharmila Hemanandh3 1UG
student, Department of ECE, JEPPIAAR SRR Engineering College, Tamil Nadu, India student, Department of ECE, JEPPIAAR SRR Engineering College, Tamil Nadu, India 3Assistant Professor, Department of ECE, JEPPIAAR SRR Engineering College, Tamil Nadu, India 2UG
---------------------------------------------------------------------***--------------------------------------------------------------------Abstract - Multiplication of complex number finds numerous applications in Science and Engineering. Complex multiplication design can be the most time and area consuming operations in DSP. Hence, an attempt is made in this paper to reduce the complexity of complex multiplier by using Vedic mathematical techniques. Vedic mathematics contains 16 sutras which are mathematical short hands for range of operation covering basic arithmetic's, algebraic and trigonometric operation to more complex calculus operation. Out of 16 sutras two sutras are used for multiplication. Traditionally, the complex multiplier suffer from low speed due to more number of partial product and carry propagation. A complex multiplier is designed using Urdhva Tiryagbhyam sutra. The results prove that the proposed vedic multiplier is faster than the conventional multiplier. A 8 point radix 2 Decimation in Frequency(DIF) Fast Fourier Transform(FFT) algorithm is implemented using the proposed vedic multiplier . Key Words: Complex Multiplier, Vedic Mathematics, Urdhva Tiryagbhyam sutra, Partial product reduction,Fast Fourier Transform. 1.INTRODUCTION FFT is a highly elegant a
nd efficient algorithm, which is still one of the most used algorithms in speech processing, communications , frequency estimations, etc, one of the most highly developed area of DSP. FFT is an algorithm proposed by Cooley and Turkey in 1965.It is a highly efficient procedure for computing the DFT[1] of finite series and requires less number of computations than that of direct evaluation of DFT. FFT is based on decomposition and breaking the transforms and combining them to get the total transform. It makes use of symmetry and periodicity properties of twiddle factor WN to effectively reduce the DFT computation time[2] . Addition and multiplication are the two major arithmetic operations involved in the computation of the FFT algorithm. The design of the complex multiplier influences the overall computational complexity of the FFT algorithm. Hence vedic mathematics is used in the design of complex multiplier to reduce the computational complexity, area and power. In this paper a complex multiplier is designed using Urdhuva-Tiryagbyam sutra. Š 2017, IRJET
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1.1 VEDIC MATHEMATICS Vedic mathematics is a book written by the Indian Hindu Priest Bharati Krishna Tirthagi and first published in 1965[3]. Vedic mathematics is a collection of techniques, sutras to solve mathematical arithmetic in easy and faster way It consists of 16 sutras (Formulae) and 13 sub-sutras (sub-formulae) which can be used for problems involved in arithmetic, algebra, geometry and calculus[4]. From all the 16 sutras in the ancient vedic mathematics Nikilam Navatashcaramam Dashatah sutra and Urdhuva-Tiryagbyam sutra can be used for complex number multiplication[5]. The meaning of this Nikilam is "All from 9 and the last from 10". Nikilam sutra can also be applied to large numbers. Urdhuva-Tiryagbyam method is another method used for multiplication. Urdhuva means " Vertically and crosswise". Vertically means straight above multiplication and crosswise means diagonal multiplication and taking their sum. It has the advantage that it reduces the multi bit multiplication into single bit multiplication and addition[6]. This results in the generation of all the partial products in one step which further reduces carry propagation that occurs from LSB to MSB during the process of addition. . It is based on the concept that generation of all partial products can be done and then concurrent addition of these partial products is performed. The parallelism in generation of partial products and their summation is obtained using UrdhvaTiryakbhayam.. The Multiplier based on this sutra has the advantage that as the number of bits increases, gate delay and area increases at a slow pace as compared to other conventional multipliers. 1.2 COMPLEX MULTIPLIER Multiplication of two complex number is a very frequent operation in many signal processing algorithms. A complex multiplier is a combination of real number and imaginary number.[7] In general two complex numbers (a+jb) and (c+jd) are multiplied as follows (a+jb)(c+jd)=(acbd)+j(ad+bc). Fig. 1 shows the block diagram of the complex multiplier. Here 4 multipliers and 3 adder/subtractor blocks are used. At first the two complex numbers (a+jb) and (c+jd) are fed as input to the multiplier as shown in Fig.1 . The multiplier generates the partial products ac, bd, ad and bc. Then the sum and the difference between the partial ISO 9001:2008 Certified Journal
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