International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395 -0056
Volume: 04 Issue: 03 | Mar -2017
p-ISSN: 2395-0072
www.irjet.net
Delay Optimized Full Adder Design for High Speed VLSI Applications Tincy Charles1 , Mohammed Salih K K2 Mtech Scholar, Department of ECE, GECI, Kerala, India Assistant Professor, Department of ECE, GECI, Kerala, India 1
2
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Abstract - The most widely used arithmetic operation in
digital applications is addition. Full adder is the most important building block in digital signal processors and controllers as it is used in arithmetic logic circuit(ALU) , in the floating point unit and in case of cache or memory access address generation. As density of IC chip increases, power consumption also increases. Hence low power designs is the primary requirement in the VLSI field. Reducing delay of a digital circuit is an important topic in logic design for efficient implementation of adder. In this paper a hybrid CMOS full adder circuit designed using both transmission gate and complementary metal oxide semiconductor(CMOS) is implemented and a modified version of this full adder is proposed. Design was implemented using Cadence Virtuoso Tools in 180nm and 90nm technology. Then comparison is done against these full adders in terms of power, speed and power delay product. Key Words: CMOS,TG, Power Delay Product
1.INTRODUCTION Adders are one of the major components in digital systems, as they are widely used in basic digital operations such as division, multiplication and subtraction.As addition forms the basis of many binary operations, adder circuits are of great interest in digital design. Deep submicron CMOS technologies are used to explain the challenging criteria of the emerging high-speed and low-power communication IC chips. Analyzing any digital system, we can see addition is a basic operation. A heuristic approach, known as hybrid adder models is proposed to save power at low transistor sizes.A wide variety of adder circuits have been proposed in literature, with the purpose to fulfill the various area, power and speeds requirements of implementations[3]. Designers move their attention to design an efficient full-adder, which operates with the minimum power consumption and high speed. Power dissipation depends upon the switching activity, wire capacitances, node capacitances and control circuit size.
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Full adders can be classified into static and dynamic full adders. Static full adders are reliable, require less power but on the cost of area[2]. While dynamic full adders have high speed operation, high driving capability, low power, low input capacitance and but power dissipation due to higher switching activities and they require N+2 transistors for N input logic function instead of 2N transistors required by standard adder as they use only NMOS transistors and due to absence of PMOS input capacitance is lower but dynamic full adder suffer from complexity, charge sharing and high power requirement due to high switching so a hybrid logic style will embed the both static and dynamic full adder to get better results.
2. REVIEW OF VARIOUS LOGIC STYLES Static CMOS logic style is known for its better power efficiency,high noise margin,no static power dissipation.It is more robust for transistor sizing and voltage scaling[4].The disadvantages include higher delay and large capacitance[3].Various static logic styles include PseudoNMOS logic,Transmission logic,Pass Transistor logic etc. Pseudo-NMOS logic style adder replace the pull-up block with single PMOS transistor thus reducing the number of gates. Thus it reduces the capacitance and improves the speed. The Rand asymmetrical noise margin.TransmissionGate(TG) Full Adder uses XOR gate.It acts as a high-quality switch with low capacitance and resistance[5],[6].It is one of the members of the ratio less logic family as the DC characteristics are independent of the input levels. Complementary Pass Transistor Logic (CPL) adder implements logic functions with NMOS-only.Its advantages include differential inputs/outputs,circuit modularity and simplicity[7]. It can be efficiently realized with small number of transistors. The disadvantages of CPL is reduced higher static power consumption and noise margin. Double Pass Transistor Logic (DPL) adder is a modified version of CPL that is suitable for low-voltage application[7].DPL has balanced input capacitances, therefore reducing the dependence of the delay on the input data. DPL also provides full logic swing due to the use of PMOS gates as well as NMOS, and the dual current driving ability of DPL compensates for the additional PMOS gates [5]. The disadvantages of DPL is
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