International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395 -0056
Volume: 04 Issue: 03 | Mar -2017
p-ISSN: 2395-0072
www.irjet.net
“Optimizing Data Encoding technique for Dynamic Power reduction in Network on Chip” M. Vijaya Prasad PG Scholar Dept. of ECE
V. Keerthi Kiran
K. Pradeep
Assistant Professor
Associate Professor
Dept. of ECE
Dept. of ECE
Baba Institute of Technology
Baba Institute of Technology
& Sciences, Visakhapatnam
& Sciences, Visakhapatnam
Baba Institute of Technology & Sciences, Visakhapatnam
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Abstract:-
1.Introduction :
As the technology shrinks, the power consumed by the links of a Network On Chip(Noc) is starts to participate with the power dissipated by the elements of the communication systems like Network Interfaces(NIs), routers etc. In this paper we have presented the optimizing data encoding technique by different schemes geared towards to reduce the power dissipated by the links of Network on Chip, that optimizes the on-chip communication system not solely in terms of performance but also in terms of power.
As silicon technology scales to next technology, however power demand becomes a primary factor in communication systems. In fact, over 50% of the entire dynamic power is dissipated in interconnects in current processors, and this will be expected to rise to 65%–80% over the succeeding years. The power dissipation is proportional to the switching activity, so reducing the bus switching in an efficient way to reduce the bus power consumption. System-on-Chip is a novel illustration supposed for Network-on-Chip design. NoC based systems contain numerous asynchronous clocks with the aim of today’s composite SoCs. NoCs that provides asynchronous communication, scalability, reliability for the NoC paradigm. The essential plan of network-on-chip becomes additional capable owing to its performance, power and scalability requirements for a SoC device. The dynamic power consumption in a NoC grows linearly with the sum of bit transitions in successive information packets sent through the interconnect design to scale back power dissipation in NoCs, in both wires and logic, is to reduce the switching activity by means of coding schemes.
Here, within the proposed work the encoder in LDPC is replaced with our data encoding schemes therefore as to cut back the power consumption in the LDPC techniques. Three schemes join to reduce the dynamic power of the NoCs data path by minimizing the number of bit transitions. Different transitions like odd, even and full are taken into consideration. During this experiment determined that the proposed technique yields sensible ends up in dynamic power reduction.
Index terms-- Data Encoding , Low power, Interconnection on chip, Network Interfaces, Nework-on-Chip(NoC), Low Density Parity Checker (LDPC), Power analysis.
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Low density parity check code is an error correcting code used in noisy communication channel for decreasing the probability of loss of information. With LDPC, this probability can be minimized to as tiny as desired, so the data transmission rate is as |
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