International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395 -0056
Volume: 04 Issue: 03 | Mar -2017
p-ISSN: 2395-0072
www.irjet.net
REVIEW ON OPTIMIZED AREA,DELAY AND POWER EFFICIENT CARRY SELECT ADDER USING NAND GATE Pooja Chawhan, Miss Akanksha Sinha, 1PG
Student Electronic & Telecommunication Shri Shankaracharya Technical Campus, Junwani, Bhilai 2Assistant Professor Dept of E&I Shri Shankaracharya Technical Campus Junwani,Bhilai, Chhattisgarh, India
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Abstract - In the modern digital life the increased
important role of digital design invites new challenges of digital media. In the electronic field, carry select adder is one of the fastest adder used in microprocessor and digital signal processing to perform fast airthmatic operation. The structure of carry select adder require more area because its internal structure consist of two ripple carry adder (RCA) and multiplexer. The conventional carry select adder and binary to excess-1 convertor to require more area, power and redundant logic. In this proposed work significantly reduce area, power and redundant logic operation present in conventional carry select adder. The new logic formulation technique using NAND gate optimize area, it obvious to reduce the power consumption is most important area of research in VLSI design. In practice, this is advantageous since NAND gate chip are particularly easy to make and are very cheap. The NAND gate has lesser delay than NOR and it is easier to fabricate. The NAND gate have better power performance. Key Words: Adder, arithmetic unit, low-power design, universal gates, redundant logic, Binary to Excess-1 converter.
1.INTRODUCTION In digital electronic, the carry select adder are most widely used in digital system and play a important role of heart for many computational circuit and other complex circuit, based on addition .it is most widely used in many data processor to perform one of the speedest adder and main component of airthmatic unit. the design of digital adder optimize area, delay and reduce the power consumption is most important area of research in VLSI system design. The low-power, high performance and area efficient VLSI system design most widely using in mobile device, multi standard and wireless receiver, biomedical instrumentation, satellite and mobile phone etc. The ripple carry adder used a simple design structure. It is connected in parallel to N number of bit. Which allow to fast design but carry propagation delay is more. carry look ahead adder is fast adder used in digital logic. Carry look ahead adder solve the problem of ripple carry adder it reduce the carry propagation delay and improve the speed but the carry look block are very complicated. A conventional carry select adder used to two Š 2017, IRJET
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Impact Factor value: 5.181
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ripple carry adder and provide less carry propagation delay as compare to RCA. The area and power of carry select adder can be reduce with the help of BEC-1 convertor. The basic idea of BEC-1 convertor used the transistor level. When the advantage of transistor level used to less number of transistor than the BEC.
The proposed carry select adder design optimize the area, delay and power consumption than the existing carry select adder design. It can be implemented with the help of universal NAND gate. A universal NAND gate can be used any type of Boolean function without use to other gate. The NAND gate has lesser delay than NOR gate and NAND gate chip are easy to make and very cheap. The NAND gate are easier to fabricate and this basic gate are used in all IC digital logic families. The NAND gate have better performance as compare to other gate.
2. LITERATURE SURVEY A number of research paper and various journal and conference. We are studied and survey of existing technique. In digital electronic increase the speed of digital system. As we know different type of adder ripple carry adder, carry look ahead adder, carry select adder, conventional carry select adder, SQRT carry select adder etc. B.Ramkumar and H.M Kittur et.al 2012 proposed low power and area efficient carry select adder. It is used to reduce area and power consumption of CSLA. This proposed work use a simple and efficient gate level modification to optimize area and power. The proposed modification 8-,16,32-,64-b SQRT CSLA structure compared with exiting regular SQRT CSLA. The proposed design optimize area and power as compare to regular SQRT CSLA with more in delay. The proposed design of CSLA is better than the regular SQRT CSLA[1]. Shivani Parmar and Kiratpal Singh et.al 2013 proposes the area and power efficient carry select adder. When the carry select adder is fast adder used in many digital signal processing system and microprocessor. In proposed modified carry select adder are reduce the larger area and power consumption with small speed. The number of logic gate are used to BEC is less than the RCA design.the ISO 9001:2008 Certified Journal
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