International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395 -0056
Volume: 04 Issue: 3 | Mar -2017
p-ISSN: 2395-0072
www.irjet.net
Digital Static Timing Path Analyzer for DSCH Program Vishal D. Khulape 1, Dr. Vijay N. Patil2, Vinay Sharma3 2Professor,
1PG
student, Pimpri Chinchwad College of Engineering Akurdi Pune Dept. of E & TC, Pimpri Chinchwad College of Engineering, Akurdi Pune, Maharashtra, India 3Technical Director, Ni Logic Pvt Ltd, Kothrud, Maharashtra, Pune
---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract - Miniaturization of transistor size comprises in
We studied the problems in timing analysis feature of DSCH tools are: different timing path, understanding timing paths through image, calculation of logical path delay.
increasing the complexity of digital circuit design in DSM era. So, successful development of an ASIC depends on accurate modeling of its operation and designing a circuit to be logically correct is simple whereas producing an accurate timing model is critical. IC’s are computer representation of the physical device so the designer’s role is to design models characteristics with precise accuracy as actual silicon behaves. Timing analysis is an integral part of ASIC design flow. It is important to note that the CAD tools are designed to offer an automation of process to minimize the circuit design cycles, the designer is still a human being who controls how the tool will perform. CAD tools are also susceptible to GIGO: Garbage In Garbage Out, Phenomenon. Thus, the designers are still need to understand the nuances of design methodologies, using CAD tools to obtain optimized design. This paper describes the theory and the procedure applied for timing analysis in EDA tool i.e. DSCH which is a part MICROWIND chip design tool.
The dissertation of this paper is arranged as, in section-I overview of timing verification and in the section II path delay calculation with an example is demonstrated. In section III the basics of static timing analysis and the dearth of timing path analysis in DSCH tool is presented. In next section IV, the proposed method and the last section the results obtained as well as the extended work is described.
1.1 Overview of Timing Verification Fig.1 shows a typical ASIC design flow. There are major parts of design flow are as: design entry, design implementation, design verification, and IC production. This is general design flow, and timing verification is part of design verification.
Key Words: Static Timing Analysis, Timing Path, Critical Delay, EDA tool etc.
Design Entry
1 INTRODUCTION Design Implementation As the increase in complexity of digital designs and the requirement of timing measurements in various design stages make static timing analysis critical. Each design stage utilizes static timing analysis to evaluate the system performance, and then optimizes the design accordingly. An accurate and efficient timing analysis package is crucial for the success of the whole design process. Timing is important because just designing the chip is not enough; we need to know how fast the chip is going to run, how fast the chip is going to interact with the other chips, how fast the input reaches the output etc.
Design Verification IC Production Fig.1 Typical ASIC design flow Functional simulation is the important step after a design is completed. Functional simulation tests the functional requirement of design. Timing verification determines if the design meets the timing requirements. Dynamic timing analysis and static timing analysis are the methods for verification of timing.
There are number of chip design EDA tools that support timing analysis of the design such as PrimeTime from Synopsys, Pearl from Cadense and Chronology’s TimingDesigner etc. DSCH is dedicated to provide innovative EDA solutions to mixed signal IC schematics.
© 2017, IRJET
|
Impact Factor value: 5.181
Dynamic timing analysis requires a set of input vectors to check the timing characteristics in a design. It can verify the functionality as well as the timing requirement. It
|
ISO 9001:2008 Certified Journal
|
Page 674