International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395 -0056
Volume: 04 Issue: 3 | Mar -2017
p-ISSN: 2395-0072
www.irjet.net
Design & implementation of 16 bit low power ALU with clock gating Kajal shinde1,Priya marathe2,Pallavi Kesarkar3,B.Lakshmipraba4 1,2,3BE
Student (DYPIEMR ,Akurdi) Professor 1,2,3,4 Dept. of Electronics & Telecommunication Engineering, DYPIEMR, Akurdi, Pune, Maharashtra, India 4Assistant
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Abstract - This project presents the need of ALU in low
power concern .Out of the various methods of controlling the low power clock gating is one of the method has proven to be the most versatile. The overall scheme of implementing low power ALU has been presented .CPUs in general purpose personal computers ,such as desktops ,laptops dissipate significantly more power in the order of few watts because of their higher complexity and speed.ALU is a fundamental block of CPU .It does all the processes which are related to all arithmetic and logical operation .As these all operations become more complex, more expensive and requires more space and contributes more power consumption of that ALU is a prime concern while designing of CPU . Key Words: ALU, VHDL, Clock Gating, FPGA, Sparten3E
1. INTRODUCTION Here, main aim to obtain faster device performance and the optimization for lower power dissipation .The ideal design is the one which has less power, less area but it has highest device performance .But, these parameters are contradictory with each other .So, better solution has to be specified to maintain tradeoff between these all parameters . Now-a-days microprocessors, microcontrollers are designed to be operated at low power with a maximum speed and also in the portable devices, there is more necessity to improve battery life .ALU is the most commonly used module in the CPU during the execution of the instruction . In this paper, using clock gating technique a 16 bit ALU is designed in VHDL language .For optimization of lower power consumption .A carry skip adder is used as a primary element of the arithmetic unit .The design is stimulated in Isim simulator and finally in Xilinx Spartan 3E FPGA . Low Power ALU Design is based on application of clock gate to turn off the sub-module of ALU that is not in use by current executing instruction as decided by instruction decoder unit. According to, Clock Power consumes 50-70 percent of total chip power and will increase in the next coming generation of hardware designs at 32nm and below. Hence, reducing clock power is very important. Clock gating is a key power reduction technique used by hardware © 2017, IRJET
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designers and is typically implemented by RTL-level HDL Simulator or gate level power analyser tools. ( Power = CL × Voltage × frequency ) In equation power is directly proportional to the square of voltage and the frequency of the clock.
1.1 Dynamic power dissipation Dynamic power dissipation of CMOS circuit has two parts- dynamic switching power and short-circuit current power . Dynamic switching power is dissipated every time the logic state of the gate changes. It is represented as P = nfCLVdd2, where f is the frequency of switching, CL is the load capacitance, Vdd is supply voltage and n is the probability of switching. This power can be reduced by lowering switching frequency; however it is not desirable as it limits the speed of operation of the device. n can be reduced by reducing redundant switching activity. Vdd can also be reduced, however it leads to increased propagation delays and hence not desirable. Hence a proper tradeoff must be met between these parameters to obtain satisfactory device performance. Short circuit current power is dissipated when both the NMOS and CMOS MOSFETs are partially on, during a switching activity. In this case a direct short circuit path is momentarily formed between power supply and ground, leading to significant power dissipation. This can be controlled by regulating the slew rate and applying sharp clock edges. However, generating such a clock is difficult.
1.2 Static power dissipation Static or quiescent power dissipation is independent of the switching activity of the circuit. This is caused due to leakage current in the device during steady state. Subthreshold conduction is the reason for this power dissipation and can be controlled by biasing the MOSFETs well below their threshold voltages and using multiple threshold CMOS designs.
1.3 Clock Gating Clock power constitutes a significant portion of dynamic power. In a synchronous circuit several modules are clocked at the same time. However, at any particular instant only a ISO 9001:2008 Certified Journal
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