International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395 -0056
Volume: 04 Issue: 03 | Mar -2017
p-ISSN: 2395-0072
www.irjet.net
Permonace Modeling of Pipelined Linear Algebra Architectures on ASIC Shubhi Sharma1, Vidyadhar Jambhale2, Abhijeet Shinde3, Sivnantham S4 1M.Tech
VLSI Design, Vellore Institute of Technology, Vellore VLSI Design, Vellore Institute of Technology, Vellore 3M.Tech VLSI Design, Vellore Institute of Technology, Vellore 4Professor, Dept. of electronics Engineering, Vellore Institute of Technology, Tamil Nadu, India 2M.Tech
---------------------------------------------------------------------***---------------------------------------------------------------Abstract— The elements that characterize execution of a specific usage incorporate the engineering design, number of pipelines and memory bandwidth. Present mathematical model based on above factor is used for calculation of pipelined ASIC accelerators computational time. Linear algebra computation are the main contributors to that of total execution time as they are used for many compute intensive application. Since many combinational implementations are not feasible as their number of operating bits continue to increase so pipelined architecture has been designed for moving data swiftly. We have performed the ASIC implementation comprising of code coverage, floorplan, routing and placement. Key Words: ASIC, Pipelining, MAC, Synthesis
1.INTRODUCTION The core of these applications is frequently made out of linear algebra based math calculations, for example, dot product, matrix–matrix multiplication [1], matrix–vector multiplication [2], matrix inverse and matrix decomposition. The model parameters for this architecture is used and defined to calculate time of execution. The mathematical model is going to be based on the factors such as number of pipelined used and memory bandwidth limitations. We have performed the ASIC [4] implementations of the modules using the Verilog [3] code and synthesizing it for obtaining the floorplan.
2. DOT PRODUCT
Fig -1: Dot product presentation Here the pipeline [4] structure is defined as two multipliers and an adder that is able to calculate the dot product of two element vectors. For vectors of size N the number of pipeline used is N/2 and the number of iteration required is 1. For example, a computation using 8 element vectors will require 4 pipelines and will compute the swift operation in one iteration only. Then, the results of the multiplications are accumulated in an adder tree. Although adding more pipelines allows more work to be done in parallel. These additional adders will increase the overall latency of the architecture.
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