International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395 -0056
Volume: 04 Issue: 02 | Feb -2017
p-ISSN: 2395-0072
www.irjet.net
Review on low power high speed 32 point cyclotomic parallel FFT Processor Ku. Sujata B. Telrandhe1, Associate Prof. M. N. Thakre2 M.Tech Student, Department of Electronics and Telecommunication, B.D.C.O.E, Wardha, Maharashtra, India1 Assistant Professor, Department of Electronics and Telecommunication, B.D.C.O.E, Wardha, Maharashtra, India2 ---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract - In this paper, the review of a low power 32
point Cyclotomic parallel Fast Fourier Transform (FFT) Processor has be presented. The Fast Fourier transform is one of the rudimentary operations in field of digital signal and image processing. FFT is a technique which efficiently calculates the DFT by reducing the number of addition and multiplication operations takes place. Cyclotomic FFT is the type of FFT algorithm DFT into several convolutions. This paper shows tradeoff between area and performance. Cyclotomic FFT will help to reduce this trade off over FFT. This paper concentrates on the developments of 32-point Radix-4 FFT by using VHDL as a design entity. The parallel FFT and the combinations of pipeline FFT will be use to improve the efficiency and speed. The synthesis results will show the computation for calculating the FFT by VHDL and their performance. Key Words: fast fourier transform (FFT), Radix, VHDL, Cyclotomic, Pipeline FFT, Butterfly, Parallel FFT.
2. LITERATURE REVIEW
1.INTRODUCTION The FFT processor is widely used in mobile systems for image and signal processing applications. The requirement for low-power FFT architectures for telecommunication systems in portable form is becoming more and more important. Due to the characteristic of non-stop processing at sample rate, the pipelined FFT is the leading architecture for high throughput or low-power solutions. In pipelined architectures, power consumption is dominated by the commutator and the complex multiplier at each stage. This proposes the design of 32-points FFT processing block. The work of the project is focused on the design and implementation of FFT. This design computes 32-points FFT and all the numbers follow fixed point formatin to the frequency domain. The pipelined FFT is viewed as the leading architecture for real time applications. However, the use of only one processor element (PE) in each stage limits the throughput of pipelined FFTs. Therefore, an increased throughput requires further parallelization. pipeline architecture is a special class of FFT architecture, © 2017, IRJET
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Impact Factor value: 5.181
which is able to compute the FFT in a sequential manner as they can easily merged with sequential nature of sampling. So the architecture is suitable for real–time applications. Previous research work is based on either cyclotomic based pipelining or multiplier based parallel processing. Each of these designs have their own advantage. In our research work, we will be combining the advantages of both cyclotomic pipelining and parallel multipler in order to get the best design in terms of power and delay. Initially, a parallel multiplier based FFT butterfly unit will be created. This unit will consist of an upper and a lower node. Upper node performs addition, lower node performs subtraction. Both of these nods are combined to form a butterfly. For a 32 point FFT, we will need 16 nodes, as 1 node can process 2 inputs. The connection of these nodes will be done on the basis of cyclotomic pipelined design, where we will make sure that when stage 1 processing is done, then stage 2 starts working on the ouput of stage 1, and stage 1 starts working on the new inputs. There by improving the overall throughput and power efficiency of the system.
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In this paper entitled “Analysis and Design of Low Power Radix-4 FFT Processor using Pipelined Architecture” proposed on low power technique for fast fourier transform. This strategy for Fast Fourier Transform is an elevated form of Discrete Fourier Transform which is much simpler, effective, and faster with lesser number of computations has dominated in various fields. Several low power techniques like sign swap, sub expression elimination alongwith several area reduction techniques like “In Place” addressing, single butterfly element per stage using the pipelined architecture. Pipelined architecture with low power techniques is implemented on both radix-2 and radix-4 FFT processor and compared. Results shows that pipelined Radix-4 FFT consumes11% less power compared to radix-2 FFT for 16 point implementation. Number of clock cycles required for the radix-r algorithm is given by (N/r)/(log N), so for computing 64 point FFT radix-4 algorithm requires 48 clock cycles where to implement the same 64 point FFT radix 2 algorithm requires 192 clock cycles which means radix-2 algorithm is 4 times slower in comparison with the ISO 9001:2008 Certified Journal
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