International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395 -0056
Volume: 04 Issue: 02 | Feb -2017
p-ISSN: 2395-0072
www.irjet.net
REVIEW PAPER ON 32-BIT RISC PROCESSOR WITH FLOATING POINT ARITHMATIC Mrudul S.Ghaturle1, Prof.R.D.Kadam2 M-Tech (Student) ,E&T Department, BDCOE, Sevagram,Maharashtra,India1 Assistant Professor, E&T Department, BDCOE, Sevagram,Maharashtra,India2 ---------------------------------------------------------------------***--------------------------------------------------------------------as compared to CISC.RISC design ideally suited to Abstract - The paper proposes 32-bit RISC processor with participate in a powerful trend in the embedded floating point arithmetic for high speed and low power Processor market - the "system-on-a-chip". The most consumption .It is having five stage pipelining which is common RISC microprocessors are ARM, SP ARC, MIPS designed using VHDL. Number of instruction are designed for and IBM's PowerPC. Some CPUs have been specifically this processors. We use 5-stage pipelining which involves designed to have a very small set of instructions – but instruction fetch module, instruction decode, module, these designs are very different from classic RISC execution module, memory i/o and write block. designs, so they have been given other names such as minimal instruction set computer (MISC), Key words: RISC processor, Floating point arithmetic, or transport triggered architecture (TTA), etc. Despite VHDL, Xilinx, Instruction set. many successes, RISC has made few inroads into the desktop PC and commodity server markets, 1.INTRODUCTION where Intel's x86platform remains the dominant processor architecture .Outside of the desktop arena, 1.1 Processor however, the ARM architecture (RISC) is in widespread use in smartphone, tablets and many forms of A processor is the logic circuitry that responds to and embedded device. It is also the case that since the processes the basic instructions that drive a computer. Pentium Pro (P6) Intel has been using an internal RISC The term processor has generally replaced the term processor core for its processors. While early RISC central processing unit (CPU). The processor in a designs differed significantly from contemporary CISC personal computer or embedded in small devices is designs, by 2000 the highest performing CPUs in the often called a microprocessor. Types of processors RISC line were almost indistinguishable from the according to the Instruction set:highest performing CPUs in the CISC line[9]. 1.1.1 CISC (Complex instruction set computing): The CISC concept is an approach to the Instruction Set 1.2 Floating Point Architecture (ISA) design that emphasizes doing more with each instruction using a wide variety of In computing, floating point is the formulaic addressing modes, variable number of operands in representation that approximates a real various locations in its Instruction Set. As a result, the number so as to support a trade-off between range instructions are of widely varying lengths and and precision. A number is, in general, represented execution times thus demanding a very complex Control Unit, which occupies a large real estate on approximately to a fixed number of significant Chip[9]. digits (the significant) and scaled using an 1.1.2 RISC (Reduced instruction set computing) : The RISC Processor have reduced number of Instructions, fixed instruction length, more general purpose registers, load-store architecture and simplified addressing modes which makes individual instructions execute faster, achieve a net gain in performance and an overall simpler design with less silicon consumption Š 2017, IRJET
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exponent in some fixed base; the base for the scaling is normally two, ten, or sixteen.
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