International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395 -0056
Volume: 04 Issue: 02 |Feb -2017
p-ISSN: 2395-0072
www.irjet.net
Design and Implementation of Multiplier using Advanced Booth Multiplier and Razor Flip Flop Shubhangi Ramannawar1, Deepak Kumar2 1M.Tech.
Scholar, Department of Electronics & Communication Engineering, Vidhyapeeth Institute of Science & Technology Bhopal, India (e-mail: shubhangi.ramannawar@gmail.com). 2Assistant Professor, Department of Electronics & Communication Engineering, Vidhyapeeth Institute of Science & Technology Bhopal, (RGPV,Bhopal) India (e-mail: deepak.kirar@gmail.com). ---------------------------------------------------------------------***--------------------------------------------------------------------1. INTRODUCTION A traditional method to reduce the aging effect is processing with its various other applications made overdesign, including such things as guard-banding and gate digital multipliers to play major role in technology. over sizing; however, this approach can be very pessimistic Many researchers are working to design multipliers and area and power inefficient. For eliminate this problem, which offer either of the following design targets – high number of NBTI-aware methodologies have been proposed. speed, low power consumption and less area. An NBTI-aware technology mapping technique was Furthermore, the negative bias temperature instability proposed in to pledge the performance of the circuit during effect occurs when a pMOS transistor is under –ve bias its lifetime. In an NBTI-aware sleep transistor was planned (Vgs = −Vdd), increasing the Vt (threshold voltage) of to decrease the aging effects on pMOS sleep-transistors, and the pMOS transistor, and declinement in multiplier the life time stability of the power-gated circuits under consideration was made better. Wu and Marculescu [9] speed. Similarly, +ve bias temperature instability, proposed a joint logic restructuring and pin reordering occurs when an nMOS transistor is under positive bias. method, which is based on detecting functional symmetries Both the effects directly hinder the multiplier speed by and transistor stacking effects. degrading transistor speed, if this problem occurs for long time then the system may fail due to timing No variable-latency multiplier architecture that considers the aging effect and can adapt dynamically has violations. To overcome the timing violations, Variable been done. There are many multiplier architectures latency technique is used. Therefore, it is important to developed to boost the speed of algebra. Booth algorithm is design efficient high-performance multipliers. the most effective algorithm used for faster performances. It In this paper, we propose a high speed multiplier is introducing a high performance multiplier using Modified design using Modified booth multiplier algorithm. The Radix4 booth algorithm with Redundant Binary Adder to get multiplier designed using booth algorithm have two high speed. A comparative study between column multiplier 16-bit input and 32-bit output and is able to provide and booth algorithms in terms of power consumption, delay, higher throughput through the variable latency and can and area is discussed in this work. adjust the AHL circuit with help of Razor flip flop to Digital multipliers are the most complex and critical mitigate performance degradation that is due to the arithmetic functional units in many applications, such as the aging effect. The design and implementation of Fourier transform, discrete cosine transforms, and digital Efficient Multiplier Design using Advanced Booth filtering. The through put of these applications rely on Algorithm and Razor Flip Flop. The proposed multipliers, and if the multipliers are too slow, the architecture is quite different from the Conventional performance of entire circuits will be reduced. Parameters method of multiplier like row/column bypass that degrade the multiplier speed are, the negative bias temperature instability (NBTI) effect which occurs when a multiplier. The proposed architecture is simulated and pMOS transistor is under negative bias (Vgs = −Vdd), implemented on XilinxISE 14.2
Abstract – The advancement in digital signal
Key Words: NBTI (Negative Bias Temperature Instability), PBTI (Positive Bias Temperature Instability), Modified Booth Algorithm, Adaptive Hold Logic (AHL), TDDB (Time-Dependent Dielectric Breakdown), BTI (Bias Temperature Instability).
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increasing the threshold voltage of the pMOS transistor, and reducing transistor switching speed. On the other hand, positive bias temperature instability (PBTI), occurs when an nMOS transistor is under positive bias. [6]
NBTI effect results from a association of hole trapping in oxide defects and formation of interface states at the channel oxide interface (Schroder and Babcock 2003; Kaczer et al. 2008; Grasser and Kaczer 2009). PBTI is supposed to come from electron trapping in preexistant oxide traps, combined ISO 9001:2008 Certified Journal
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