International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 12 Issue: 05 | May 2025
p-ISSN: 2395-0072
www.irjet.net
ANALYSIS OF MULTIPLIERS AND PROPOSAL OF A DESIGN OF VLSI ARCHITECTURE USING HYBRID MODIFIED BOOTH MULTIPLIER S. Gajendran1, G. Prabhakaran2 P.G. scholar, Department of ECE, Nandha Engineering College, Erode, Tamilnadu, India1 Assistant Professor, Department of ECE, Nandha Engineering College, Erode, Tamilnadu, India2 -------------------------------------------------------------------------***----------------------------------------------------------------------1.1 COMPARISON OF DIFFERENT MULTIPLIERS Abstract: Compact Space and Minimal Power VLSI circuits are the standard for creating energy-efficient, high-performance, and small devices. Digital signal processing, microprocessors, and microcomputer applications all heavily rely on multipliers. In this design, we analysed and compared various multiplier types, including Wallace trees, arrays, and Booth multipliers. By using partial product reduction, multipliers can be designed to increase the creation of complex circuits and their analysis. Any algorithm for multiplying integers should aim to minimise the partial product summation. Among the most well-liked and effective algorithms is the Booth technique.
An electronic hardware circuit used in computers or digital electronics is called a binary multiplier. Binary adders are used in its acquisition. The following are the guidelines for binary multiplication. 1. The product will be the same as the multiplicand and will just be copied down if the multiplier digit is 1. 2. The product is zero if the multiplier digit is zero. Figure 1 illustrates the n X n multiplication algorithm
Keywords: Array, Wallace and Booth multipliers, Encoding, Decoding, CSA, MAC, CPA
1. Introduction Multipliers are essential for processing digital signals in real time as well as for several other processes. The design of multipliers that offer increased speed, reduced power consumption, regular layout and, therefore, a small area, or even a combination of these in a single multiplier, has been attempted and is still being attempted by numerous researchers. This makes the multipliers applicable for a variety of increased speed, reduced power, and compact VLSI prosecutions. The Booth technique and the Modified Booth algorithm, which minimise the partial products (1). It is evident that there is a desire for design patterns for digital systems that have low power consumption and high increment (2). We propose to redesign the existing. We suggest utilising a carry to redesign the becoming twofold multipliers. We propose to redesign the existing. By employing a carry look ahead adder, we suggest redesigning the being double multipliers. We obtain an efficient design in terms of detention optimisation by employing this method. The suggested approach produces a superior result in relative research where some of the variables are multipliers (3), (4). Verilog HDL is used to enforce the designs.
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1.1.A. Array multiplier Array multipliers are widely recognised because of their regular structure. Add and shift is the algorithm that multipliers use. Multiplying the multiplicand by one multiplier bit yields each and every partial product. The partial products are added after being moved in accordance with their bit ordering. With a standard carry propagate adder, the addition may be completed. A four-bit combinational multiplier consists of half adders, full adders, and AND gates. Two figures that are m and n bits wide, independently, allow us to generalise this. A series of m n AND gates operates in resembling to induce m n summands. For an n x n multiplier, thus, n half-adders, n (n - 2) complete adders, and 2n AND gates are demanded (5). n-1 adders, where n
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