International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395 -0056
Volume: 04 Issue: 05 | May -2017
p-ISSN: 2395-0072
www.irjet.net
Implementation of NoC Router and its Architecture Arshi Nazish1, Waseem Khanooni2 1M.Tech Student , Department of Electronics 2Assistant Professor, Department of Electronics S.B.Jain Institute of Technology,Management and Research,Maharashtra,India. -----------------------------------------------------------------------------***-----------------------------------------------------------------------Abstract - An Network-on-Chip is a new paradigm of elements (PEs), network interfaces (NIs), routers(R) and communication network into System-on-Chip (SoC). It channels. The PE and Nis comprise the architecture. The overcomes the problems of traditional bus-based SoC and NI packetizes data before traversing through the NoC. meet the communication requirement of next SoC.. It Each PE is attached to NI that connects the PE to local provides efficient communication and the data is routed router. The data packet transmission takes place between through the networks in terms of packets. The routing of sources PE to destination PE. During transmission the data is mainly done by routers. A router is one of the most packet is forwarded hop by hop on the network depending important communication back bone in NoC. The design is on the decision made by the router. The router further implemented in VHDL and simulated in Xilinx ISE Design contains switches and buffer. The buffer is also an important parameter which consumes around 64% of Suite 13. total node leakage power. A node comprises of a router Key Words: Network-on-chip(NoC), System on chip(SoC), and the link associated with it. In router, the packet is first Field Programmable Gate Array(FPGA), received and stored at input buffer. The control logic of Router,Architecture. router makes the routing decision and channel arbitration and finally the selected packets traverse to next router 1. INTRODUCTION through a crossbar. This process is repeated until the packet reaches its destination. Several Processing NoC is a method to design the communication subsystem Elements (PEs) together comprise a generic NoC between intellectual property cores in a SoC. System on implementation. The Processing Elements (PEs) can be chip uses dedicated buses for communicating with the various processors, memory elements and dedicated resources. Using buses as communication strategy does hardware like audio cores, video cores, wireless not give any flexibility for the needs of communication. transceivers etc. Each PE is linked to a local router through Secondly using shared buses does not scale very well as a Network Interface (NI). The NI can be used to packetize the number of resources increases in number. These or de-packetize the data into or from the underlying drawbacks have been overcome in Network-on-chip by interconnection network. Router transmits the data from implementing a communication network of routers and source to its destination, using special purposed routing resources and by using a packet-based communication algorithms and control flow mechanisms. network. Implementation medium has highly affected the configurations of SoCs and their interconnect mechanisms in term of cost and performance. NoC is becoming popular as it reduces the feature sizes and increasing use of parallel architectures. Field Programmable Gate Array (FPGA) has gain popularity over Application Specific Integrated Circuits (ASICs) in several contemporary applications because of its advantages such as low development cost and the short time required to market, Secondly, FPGA is ease to upgrade and have suitability for research purposes, given that they provide fast design cycle and immediate results. 2. NoC ARCHITECTURE Various interconnection schemes such as crossbar, buses and NoCs are currently in use. Crossbar and buses have poor scalability because of more number of processing elements. As the number of elements increases, the performance of the system degrades dramatically. Due to these disadvantages, now a days, Network –on chip is generally being used which consists of processing
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Fig 1.Generic NoC Architecture 3. ROUTING ALGORITHM The routing algorithm defines the path to be followed by a packet to travel from source router to destination router.
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