International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 12 Issue: 04 | Apr 2025
p-ISSN: 2395-0072
www.irjet.net
High-Performance of Squaring Circuit Design Using Novel Architecture S. Senthazhai1, V. Kokila2, P. Janani3, M. Keerthana4, A. Rajeshwari5, S. Deepa6 Associate Professor1, Assisstant Professor2, UG Scholars 3,4,5,6, Department of Electronics and Communication Engineering, Krishnasamy College of Engineering and Technology, Cuddalore district, Tamil Nadu, India. ---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract - This paper presents a novel squaring circuit
The rest of the paper is organized as follow .section II presents the background and motivation for the proposed work .Section III describes the proposed novel squaring circuit using an Adder. Section IV presents the simulation results and comparison with the existing system. Section V concludes the paper and discusses future work.
design using an Ripple carry adder to improve the efficiency of digital multipliers. The existing 4-bit multiplier system using squaring operation requires multiple add and shift operations, resulting in increased logical elements and delay. Consequently, the system fails to provide accurate results, instead yielding approximate values. To address this limitation, we propose a novel circuit design for 4-bit operation to compute the square, thus eliminating the need of multipliers. which provides accurate results while reducing time delay and logical elements. The proposed circuit is designed and implemented using VHDL and simulated using Altera Quartus II software. The results demonstrate the superiority of the proposed circuit in terms of speed and area efficiency.
2. BACKGROUND AND MOTIVATION Digital multipliers are a fundamental component in various digital systems, including digital signal processing, cryptography, and communication systems. These systems require high-speed and low-power multiplication operations to perform complex mathematical calculations. The demand for high-speed and low-power digital multipliers has increased significantly in recent years, driven by the growing need for energy-efficient and high-performance computing systems.
Key Words: Digital Multiplier, Squaring Circuit, Adderbased Design, High-speed Digital Circuits, Low Power Consumption, VHDL Implementation.
1. INTRODUCTION
Despite the advancements in digital multiplier design, existing digital multipliers still have several limitations. For example, they consume high power, have low speed, and are complex to design. These limitations make it challenging to develop high-speed and low-power digital systems that can meet the growing demands of various applications. Therefore, there is a need to investigate new architectures and design techniques that can improve the efficiency of digital multipliers. This paper aims to address this need by proposing a novel digital multiplier design that achieves high speed and low power consumption.
The rapid growth of digital technology has led to an increasing demand for efficient and high speed digital circuits digital multiplication is a fundamental operation in digital signal processing .widely used in applications such as filtering, convolution, and Fourier transformer [1]. However existing digital multiplier require significant hardware resources and time, making them a major bottleneck in high-speed digital system [2]. The existing 4-bit multiplier system using squaring operation is typical example of this limitation. The system requires multiple add and shift operations to perform squaring, resulting in increased logical elements and delay. Specifically the existing system uses a multiplierbased approach to perform squaring which requires a significant amount of hardware resources and times [3].
3. BINARY BIT REPRESENTATION In the context of binary squaring circuitry, a fundamental concept emerges. The base value for squaring is determined by the expression 2^n-1, where n represents the number of bits for instant in a 3-bit system the base value is 100(2^3-1), while in a 4 bit system, it becomes 1000(2^4-1).this pattern continues ,with the base value increasing exponentially with the number of bits.
To Address this limitation we propose a novel squaring circuit using adder the proposed circuit is designed to minimize the number of logical elements and delay making it suitable for high speed digital applications the proposed circuit uses an adder-based approach to perform squaring, which reduces the hardware resources and time required compared to the existing multiplier based approach [4][5] .
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A notable observation arises when examining the squaring circuitry for 4-bit numbers. The base value of 1000 serves as a threshold, dividing the numerical range
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