This paper deals with the designing and verification of first in first out (fifo) using verilog. A FIFO is a memory queue
which controls the data flow between two modules. It has the capacity to trigger different flags according to the status of the
FIFO such has empty fifo status, half read fifo status, half written fifo status, full fifo status. Both the reading and writing
operation can be performed simultaneously as it has dual port memory. After the completion of designing and simulating it on
xilinx vivado this report also covers the verification carried out in modelsim. A detailed discussion on the architecture of each
module that is writing module, reading module and memory array along with the various test benches and waveforms of
simulation and verification is included in the paper.
