AXI2OCP Bridge is a component which converts the AXI signals to OCP signals. Verification is a process of
checking the design that is implemented is working according to the requirements specified. The Advanced eXtensible
Interface (AXI) protocol and Open Core Protocol are the industry standard on-chip communication protocol. AXI2OCP
Bridge helps to establish an effective communication between two components; one communicating in AXI protocol format
and the other communicating in OCP format.
The AXI2OCP Bridge acts as a Design Under Test (DUT) module for the verification environment and it is implemented using
verilog, which is a hardware description language.
The verification environment is implemented with the help of System Verilog (SV). Verifying helps in increasing the
efficiency of the design. With the use of AXI2OCP Bridge, it is easier to connect the AXI based CPU cores to other
intellectual property which are OCP based
