Dual-port RAM place a prominent role in the field of SoC design. Verification of these memories are much more
important while designing a complex system. As the rapid developments taken place in verification techniques, System Verilog
and UVM (universal verification methodology) takes a higher priority. Because assertion-based coverage can be done using
System Verilog and reusability can be achieved by UVM. In this paper, we are analysing the verification of dual port RAM under
System Verilog and UVM environment