In this paper, an efficient parallel processing architecture using Least mean square (LMS) adaptive filter based on
Distributed arithmetic (DA). The DA based LMS adaptive filter requires look up tables (LUTs) for filtering and weight updating
operations. In this scheme the LUT size is reduced to half by using the Offset Binary Coding (OBC) technique, where the
combinations of filter weights and input samples is given to the filter is done by Multiply and Accumulation (MAC) process.
The accumulation of the combinational inputs process is done by Kogge Stone Adder(Parallel Prefix Adder)instead of using
Carry Select Adder and also the usage of gates in the circuit design is get reduced and this can achieve the less area
Consumption of the proposed system. Here in the proposed system Offset binary coding technique reduces the LUT size by half
comparing with the Non-OBC technique. The algorithm is written in Verilog HDL and tested on Xilinx 14.7 ISE and the
algorithm is implemented in FPGA Vertex
