Systems Programming Exam Review
Course Introduction
Systems Programming focuses on the design and implementation of software that provides services to the computer hardware and other software applications, bridging the gap between application programs and machine-level operations. This course covers core concepts such as process management, memory management, file systems, input/output handling, and concurrency. Students will gain hands-on experience in writing low-level code, typically using languages like C or C++, and will explore system calls, interrupts, resource management, and debugging tools. Emphasis is placed on understanding how operating systems function, and on building efficient, reliable software that interacts closely with the underlying hardware.
Recommended Textbook
Computer Organization and Architecture 10th Edition by William Stallings
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Chapter 1: Basic Concepts and Computer Evolution
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Q1) When data are moved over longer distances,to or from a remote device,the process is known as data transport.
A)True
B)False
Answer: False
Q2) Control signals,interfaces between the computer and peripherals,and the memory technology used are all examples of _________ attributes.
Answer: organizational
Q3) _________ is the way in which the components are interrelated. Answer: Structure
Q4) A __________ system is a set of interrelated subsystems.
A)secondary
B)hierarchical
C)complex
D)functional
Answer: B
Q5) Often referred to as processor the ________ controls the operation of the computer and performs its data processing functions. Answer: central processing unit (CPU)
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Chapter 2: Performance Issues
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Q1) The interface between processor and ___________ is the most crucial pathway in the entire computer because it is responsible for carrying a constant flow of program instructions and data between memory chips and the processor.
A)main memory
B)pipeline
C)clock speed
D)control unit
Answer: A
Q2) Raw speed is far more important than how a processor performs when executing a given application.
A)True
B)False
Answer: False
Q3) __________ enables a processor to work simultaneously on multiple instructions by performing a different phase for each of the multiple instructions at the same time.
Answer: Pipelining
Q4) __________ Law applies to a queuing system.
Answer: Little's
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Chapter 3: A Top-Level View of Computer Function and
Interconnection
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Q1) The TL supports which of the following address spaces?
A)memory
B)I / O
C)message
D)all of the above
Answer: D
Q2) A key requirement for PCIe is high capacity to support the needs of higher data rate I / O devices such as Gigabit Ethernet.
A)True
B)False
Answer: True
Q3) With _________ transmission signals are transmitted as a current that travels down one conductor and returns on the other.
Answer: balanced
Q4) There are three important groups of DLLPs used in managing a link: flow control packets, _________________ ,and TLP ACK and NAK packets. Answer: power management packets
Q5) A __________ is a communication pathway connecting two or more devices. Answer: bus
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Chapter 4: Cache Memory
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Q1) For set-associative mapping the cache control logic interprets a memory address as three fields: Set,Word,and __________.
Q2) The __________ units execute micro-operations,fetching the required data from the L1 data cache and temporarily storing results in registers.
Q3) A line includes a _________ that identifies which particular block is currently being stored.
A)cache
B)hit
C)tag
D)locality
Q4) The cache consists of blocks called __________.
Q5) It has become possible to have a cache on the same chip as the processor. A)True
B)False
Q6) With write back updates are made only in the cache.
A)True
B)False
Q7) External,nonvolatile memory is referred to as ___________ or auxiliary memory.
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Q8) __________ memory consists of peripheral storage devices,such as disk and tape.
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Chapter 5: Internal Memory
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Q1) The advantage of RAM is that the data or program is permanently in main memory and need never be loaded from a secondary storage device.
A)True
B)False
Q2) In a _________,binary values are stored using traditional flip-flop logic-gate configurations.
A)ROM
B)SRAM
C)DRAM
D)RAM
Q3) Nonvolatile means that power must be continuously supplied to the memory to preserve the bit values.
A)True
B)False
Q4) Which of the following memory types are nonvolatile?
A)erasable PROM
B)programmable ROM
C)flash memory
D)all of the above
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Chapter 6: External Memory
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Q1) A bit near the center of a rotating disk travels past a fixed point slower than a bit on the outside.
A)True
B)False
Q2) RAID is a set of physical disk drives viewed by the operating system as a single logical drive.
A)True
B)False
Q3) The SSDs now on the market use a type of semiconductor memory referred to as flash memory.
A)True
B)False
Q4) The width of a track is double that of the head.
A)True
B)False
Q5) __________ is the standardized scheme for multiple-disk database design.
A)RAID
B)CAV
C)CLV
D)SSD
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Chapter 7: Input Output
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Q1) The Thunderbolt protocol _________ layer is responsible for link maintenance including hot-plug detection and data encoding to provide highly efficient data transfer.
A)cable
B)application
C)common transport
D)physical
Q2) The most common means of computer / user interaction is a __________.
A)keyboard / monitor
B)mouse / printer
C)modem / printer
D)monitor / printer
Q3) With a daisy chain the processor just picks the interrupt line with the highest priority.
A)True
B)False
Q4) Because the 82C55A is programmable via the control register,it can be used to control a variety of simple peripheral devices.
A)True
B)False
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Chapter 8: Operating System Support
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Q1) The ________ scheduler is also known as the dispatcher.
A)long-term
B)medium-term
C)short-term
D)I / O
Q2) A _________ system works only one program at a time.
A)batch
B)uniprogramming
C)kernel
D)privileged instruction
Q3) Privileged instructions are certain instructions that are designated special and can be executed only by the monitor.
A)True
B)False
Q4) A _________ is a collection of memory regions.
A)APX
B)nucleus
C)domain
D)page table
Q5) Early computer systems presented two main problems: setup time and _____.
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Chapter 9: Number Systems
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Q1) In the number 472.156 the 2 is the _________.
A)most significant digit
B)radix point
C)least significant digit
D)none of the above
Q2) In a __________ number system,each number is represented by a string of digits in which each digit position i has an associated weight ri,where r is the radix of the number system.
Q3) (2 x 10-1)+ (5 x 10-2)+ (6 x 10-3)represents the number _________.
Q4) Binary digits grouped into sets of four bits are called a _________.
Q5) Hexadecimal notation is only used for representing integers. A)True
B)False
Q6) Decimal "10" is _________ in hexadecimal.
Q7) Given ( ...a3a2a1a0.a-1a-2a-3 ...)r,the dot between a0 and a-1 is called the
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Chapter 10: Computer Arithmetic
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Q1) _________ format covers five floating-point representations,three binary and two decimal,whose encodings are specified by the standard,and which can be used for arithmetic.
Q2) The most important floating-point representation is defined in IEEE Standard _________,adopted in 1985 and revised in 2008.
Q3) "To subtract one number from another,take the twos complement of the subtrahend and add it to the minuend" is the _________ rule.
Q4) Negative numbers greater than 2-127 are called _________.
A)negative overflow
B)negative underflow
C)positive overflow
D)positive underflow
Q5) __________ format is a fully specified,fixed-length binary encoding that allows data interchange between different platforms and that can be used for storage.
Q6) If two numbers are added,and they are both positive or both negative,then _________ occurs if and only if the result has the opposite sign.
Q7) The use of subnormal numbers is referred to as _________ underflow.
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Chapter 11: Digital Logic
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Q1) The operation _________ yields true if either or both of its operands are true.
A)NOT
B)AND
C)NAND
D)OR
Q2) Combinational circuits are often referred to as "memoryless" circuits because their output depends only on their current input and no history of prior inputs is retained.
A)True
B)False
Q3) The value to be loaded into the program counter can come from a binary counter,the instruction register,or the output of the ALU.
A)True
B)False
Q4) The fundamental building block of all digital logic circuits is the _______.
Q5) The simplest form of sequential circuit is the _________.
Q6) A ________ is a register whose value is easily incremented by 1 modulo the capacity of the register.
Q7) The _________ connects multiple inputs to a single output.
Q8) The basic logical operations of Boolean algebra are AND,OR,and ________.
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Chapter 12: Characteristics and Functions
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Q1) A branch instruction in which the branch is always taken is _________.
A)conditional branch
B)unconditional branch
C)jump
D)bi-endian
Q2) Instruction types can be categorized as: data processing,data storage,control,and
Q3) ________ instructions operate on the bits of a word as bits rather than as numbers,providing capabilities for processing any other type of data the user may wish to employ.
A)Logic
B)Arithmetic
C)Memory
D)Test
Q4) Addresses are a form of data.
A)True
B)False
Q5) Zero-address instructions are applicable to a special memory organizations called a _________,which is a last-in-first-out set of locations.
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Chapter 13: Addressing Modes and Formats
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Q1) Register addressing is similar to direct addressing with the only difference being that the address field refers to a register rather than a main memory address.
A)True
B)False
Q2) For _________,the address field references a main memory address and the referenced register contains a positive displacement from that address.
A)indexing
B)base-register addressing
C)relative addressing
D)all of the above
Q3) All instructions in the ARM architecture are __________ bits long and follow a regular format.
A)8
B)16
C)32
D)64
Q4) Just as register addressing is analogous to direct addressing,________ addressing is analogous to indirect addressing.
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Chapter 14: Processor Structure and Function
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Q1) The _________ contains the address of an instruction to be fetched.
A)instruction register
B)memory address register
C)memory buffer register
D)program counter
Q2) The ARM architecture supports _______ execution modes.
A)2
B)8
C)11
D)7
Q3) It is possible to improve pipeline performance by automatically rearranging instructions within a program so that branch instructions occur later than actually desired.
A)True
B)False
Q4) Many processor designs include a register or set of registers often known as the _________ that contain status information and condition codes.
Q5) The major components of the processor are an arithmetic and logic unit (ALU)and a
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Chapter 15: Reduced Instruction Set Computers
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Q1) Microprogramming eases the task of designing and implementing the control unit and provides support for the family concept.
A)True
B)False
Q2) The difference between the operations provided in high-level languages (HLLs)and those provided in computer architecture is known as the ________.
Q3) The register file employs much shorter addresses than addresses for cache and memory.
A)True
B)False
Q4) _________ determines the control and pipeline organization.
A)Calculation
B)Execution sequencing
C)Operations performed
D)Operands used
Q5) With simple,one cycle instructions,there is little or no need for microcode.
A)True
B)False
Q6) The acronym SPARC stands for __________.
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Chapter 16: Parallelism and Superscalar Processors
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Q1) The simplest instruction issue policy is to issue instructions in the exact order that would be achieved by sequential execution (in- order issue)and to write results in that same order (in-order completion).
A)True
B)False
Q2) The essence of the ________ approach is the ability to execute instructions independently and concurrently in different pipelines.
A)scalar
B)branch
C)superscalar
D)flow dependency
Q3) ARM architecture has yet to implement superscalar techniques in the instruction pipeline.
A)True
B)False
Q4) The _________ predicts the instruction stream,fetches instructions from the L1 instruction cache,and places the fetched instructions into a buffer for consumption by the decode pipeline.
Q5) An alternative to _________ is a scoreboarding.
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Chapter 17: Parallel Processing
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Q1) Vector and array processors fall into the ________ category of computer systems.
A)SIMD
B)SISD
C)MISD
D)MIMD
Q2) _________ causes results issuing from one functional unit to be fed immediately into another functional unit and so on.
A)Chaining
B)Rollover
C)Passive standby
D)Pipelining
Q3) Snoopy protocols are not suitable for a bus-based multiprocessor.
A)True
B)False
Q4) Computer systems that fall into the _________ category have a single machine instruction that controls the simultaneous execution of a number of processing elements on a lockstep basis.
Q5) The four deployment models defined by NIST are: public cloud,private cloud,community cloud,and __________ cloud.
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Chapter 18: Multicore Computers
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Q1) ___________ states that performance increase is roughly proportional to square root of increase in complexity.
A)Pollack's Rule
B)Moore's Law
C)Amdahl's Law
D)MOESI Rule
Q2) _________ applications are characterized by the presence of many single-threaded processes.
Q3) The _________ is an example of splitting off a separate,shared L3 cache,with dedicated L1 and L2 caches for each core processor.
A)IBM 370
B)ARM11 MPCore
C)AMD Opteron
D)Intel Core i7
Q4) An advantage of using a shared L2 cache on the chip is that data shared by multiple cores is not replicated at the shared cache level.
A)True
B)False
Q5) A single piece of silicon is called a ________.
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Chapter 19: General-Purpose Graphic Processing Units
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Q1) The GPU is most efficient when it is processing as many warps as possible to keep the CUDA cores maximally utilized.
A)True
B)False
Q2) The _________ performs transcendental operations,such as cosine,sine,reciprocal,and square root,in a single clock cycle.
A)SM
B)SIMD
C)SFU
D)FMA
Q3) For about $200 you can purchase a GPU with 960 parallel processor cores for a workstation.
A)True B)False
Q4) The _________ scheduler breaks up each thread block it is processing into warps.
Q5) Because the GPU and the CPU are designed and optimized for two significantly different types of applications,their architectures differ significantly.
A)True
B)False
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Chapter 20: Control Unit Operation
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Q1) The number of machine cycles for an instruction depends on the number of times the processor must communicate with internal devices.
A)True
B)False
Q2) The _________ of a processor generates the control signals that cause each micro-operation to be executed.
Q3) In a __________ implementation the control unit is essentially a state machine circuit and its input logic signals are transformed into a set of output logic signals,which are the control signals.
Q4) The ________ is connected to the data lines of the system bus.
A)MAR
B)PC
C)MBR
D)IR
Q5) The ________ portion of the control unit issues a repetitive sequence of pulses.
A)instruction register
B)flag
C)control bus signals
D)clock
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Chapter 21: Microprogrammed Control
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Q1) A sequence of instructions is known as a ___________,or firmware.
Q2) The terms _________ microprogramming are used to suggest the degree of closeness to the underlying control signals and hardware layout.
A)hard / soft
B)horizontal / vertical
C)direct / indirect
D)packed / unpacked
Q3) A ________________ instruction depends on the following types of information: ALU flags,part of the opcode or address mode fields of the machine instruction; parts of a selected register -- such as the sign bit,and status bits within the control unit.
Q4) The degree of packing relates to the degree of identification between a given control task and specific microinstruction bits.
A)True
B)False
Q5) Microprogramming became a popular technique for implementing the control unit of CISC processors.
A)True
B)False
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