Embedded Systems
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Course Introduction
This course introduces students to the fundamental concepts and practical applications of embedded systems, which integrate hardware and software to perform dedicated functions within larger systems. Topics covered include microcontroller architecture, interfacing and communication protocols, real-time operating systems, and programming with embedded C/C++. Students will gain hands-on experience designing, programming, and debugging embedded devices through laboratory exercises and projects, preparing them for careers in fields such as consumer electronics, automotive systems, robotics, and IoT (Internet of Things) devices.
Recommended Textbook
Computer Organization and Architecture 10th Edition by William Stallings
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Chapter 1: Basic Concepts and Computer Evolution
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Q1) Changes in technology not only influence organization but also result in the introduction of more powerful and more complex architectures.
A)True
B)False
Answer: True
Q2) A common example of system interconnection is by means of a ________,consisting of a number of conducting wires to which all the other components attach.
Answer: system bus
Q3) __________ refers to those attributes of a system visible to a programmer.
Answer: Computer architecture
Q4) When data are moved over longer distances,to or from a remote device,the process is known as data transport.
A)True
B)False
Answer: False
Q5) Both the structure and functioning of a computer are,in essence, simple. A)True
B)False
Answer: True
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Chapter 2: Performance Issues
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Q1) The best-known collection of benchmark suites is defined and maintained by an industry consortium known as __________.
Answer: System Performance Evaluation Corporation (SPEC)
Q2) At the most fundamental level,the speed of a processor is dictated by the pulse frequency produced by the clock,measured in cycles per second,or _________.
Answer: Hertz (Hz)
Q3) Year by year the cost of computer systems continues to rise.
A)True
B)False
Answer: False
Q4) With __________ the processor looks ahead in the instruction code fetched from memory and predicts which branches,or groups of instructions,are likely to be processed next.
Answer: branch prediction
Q5) Workstation systems cannot support highly sophisticated engineering and scientific applications.
A)True
B)False
Answer: False
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Chapter 3: A Top-Level View of Computer Function and
Interconnection
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Q1) A key requirement for PCIe is high capacity to support the needs of higher data rate I / O devices such as Gigabit Ethernet.
A)True
B)False
Answer: True
Q2) A __________ is the high-level set of rules for exchanging packets of data between devices.
A)bus
B)protocol
C)packet
D)QPI
Answer: B
Q3) With asynchronous timing the occurrence of events on the bus is determined by a clock.
A)True
B)False
Answer: False
Q4) The most common classes of interrupts are: program,timer,I / O and ________. Answer: hardware failure
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Chapter 4: Cache Memory
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Q1) The L1 cache is slower than the L3 cache.
A)True
B)False
Q2) For random-access memory,__________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use.
A)memory cycle time
B)direct access
C)transfer rate
D)access time
Q3) In reference to access time to a two-level memory,a _________ occurs if an accessed word is not found in the faster memory.
A)miss
B)hit
C)line
D)tag
Q4) The cache consists of blocks called __________.
Q5) The three key characteristics of memory are capacity,access time,and _______.
Q6) __________ memory consists of peripheral storage devices,such as disk and tape.
6
Q7) External,nonvolatile memory is referred to as ___________ or auxiliary memory.
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Chapter 5: Internal Memory
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Q1) ___________ is a new type of Magnetic RAM,which features non-volatility,fast writing / reading speed,and high programming endurance and zero standby power.
Q2) A number of chips can be grouped together to form a memory bank.
A)True B)False
Q3) The two traditional forms of RAM used in computers are DRAM and SRAM.
A)True
B)False
Q4) A DDR3 module transfers data at a clock rate of __________ Mbps.
A)600 to 1200
B)800 to 2133
C)1000 to 2000
D)1500 to 3000
Q5) __________ works by creating resistance rather than directly storing charge.
Q6) The SDRAM performs best when it is transferring large blocks of data sequentially such as for word processing,spreadsheets,and multimedia.
A)True B)False
Q7) The simplest of the error-correcting codes is the _________ code.
Page 7
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Chapter 6: External Memory
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Q1) Data are transferred to and from the disk in __________.
A)tracks
B)gaps
C)sectors
D)pits
Q2) To increase density in a straightforward CAV system,modern hard disk systems use a technique known as __________,in which the surface is divided into a number of concentric zones.
Q3) Adjacent tracks are separated by _________.
A)sectors
B)gaps
C)pits
D)heads
Q4) When the magnetizable coating is applied to both sides of the platter the disk is then referred to as _________.
A)multiple sided
B)substrate
C)double sided
D)all of the above
Q5) Data is organized on the platter in a concentric set of rings called ________.
Page 8
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Chapter 7: Input Output
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Q1) There are four types of I / O commands that an I / O module may receive when it is addressed by a processor: control,test,write,and _________.
Q2) Bus arbitration makes use of vectored interrupts.
A)True
B)False
Q3) An I / O module must recognize one unique address for each peripheral it controls.
A)True
B)False
Q4) It is the responsibility of the processor to periodically check the status of the I / O module until it finds that the operation is complete.
A)True
B)False
Q5) The U.S.national version of the International Reference Alphabet is referred to as __________.
Q6) The rotating interrupt mode allows the processor to inhibit interrupts from certain devices.
A)True B)False
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Chapter 8: Operating System Support
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Q1) __________ allows the programmer to view memory as consisting of multiple address spaces or segments.
Q2) The five defined states for a process are: new,ready,waiting,halted,and ________.
Q3) The portion of the monitor that must always be in main memory and available for execution is referred to as the __________.
Q4) The OS must determine how much processor time is to be devoted to the execution of a particular user program.
A)True
B)False
Q5) The _________ defines the system call interface to the operating system and the hardware resources and services available in a system through the user instruction set architecture.
A)HLL
B)API
C)ABI
D)ISA
Q6) _________ paging means that each page of a process is brought in only when it is needed.
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Chapter 9: Number Systems
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Q1) Binary 0001 0000 0000 represents ________ in hexadecimal.
Q2) The decimal system is a special case of a positional number system with radix 10 and with digits in the range 0 through 9.
A)True
B)False
Q3) A number with both an integer and fractional part has digits raised to both positive and negative powers of 10.
A)True
B)False
Q4) Decimal "10" is __________ in binary.
A)1000
B)0010
C)1010
D)0001
Q5) To convert a number from binary notation to decimal notation all that is required is to multiply each binary digit by the appropriate power of ________ and add the results.
Q6) In the _________ system,10 different digits are used to represent numbers with a base of 10.
Page 11
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Chapter 10: Computer Arithmetic
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Q1) __________ is when a positive exponent exceeds the maximum possible exponent value.
A)Significand underflow
B)Significand overflow
C)Exponent overflow
D)Exponent underflow
Q2) The _________ is that part of the computer that actually performs arithmetic and logical operations on data.
Q3) Overflow is a less serious problem because the result can generally be satisfactorily approximated by 0.
A)True
B)False
Q4) Booth's algorithm performs more additions and subtractions than a straightforward algorithm.
A)True
B)False
Q5) Overflow can only occur if there is a carry.
A)True
B)False
Q6) The use of subnormal numbers is referred to as _________ underflow.
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Chapter 11: Digital Logic
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Q1) The _________ connects multiple inputs to a single output.
Q2) A _________ is a PLD featuring a general structure that allows very high logic capacity and offers more narrow logic resources and a higher ration of flip-flops to logic resources than do CPLDs.
A)SPLD
B)FPGA
C)PAL
D)PLA
Q3) A _________ is a combinational circuit with a number of output lines,only one of which is asserted at any time.
Q4) To ________ a signal is to cause a signal line to make a transition from its logically false (0)state to its logically true (1)state.
Q5) A _________ accepts and / or transfers information serially.
A)S-R latch
B)shift register
C)FPGA
D)parallel register
Q6) Each gate is defined in three ways: graphic symbol,algebraic notation,and
Page 13
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Chapter 12: Characteristics and Functions
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Q1) Which ARM operation category includes logical instructions (AND,OR,XOR),add and subtract instructions,and test and compare instructions?
A)data-processing instructions
B)branch instructions
C)load and store instructions
D)extend instructions
Q2) Most machines provide the basic arithmetic operations of add, subtract,multiply,and divide.
A)True
B)False
Q3) A branch can be either forward or backward.
A)True
B)False
Q4) A high-level language expresses operations in a basic form involving the movement of data to or from registers.
A)True
B)False
Q5) The operation of the processor is determined by the instructions it executes,referred to as _________ or computer instructions.
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Chapter 13: Addressing Modes and Formats
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Q1) __________ has the advantage of large address space,however it has the disadvantage of multiple memory references.
A)Indirect addressing
B)Direct addressing
C)Immediate addressing
D)Stack addressing
Q2) The __________ instruction set is designed to increase the performance of ARM implementations that use a 16-bit or narrower memory data bus and to allow better code density than provided by the ARM instruction set.
Q3) __________ explicitly specifies which segment register an instruction should use,overriding the default segment-register selection generated by the x86 for that instruction.
Q4) One advantage of linking the addressing mode to the operand rather than the opcode is that any addressing mode can be used with any opcode.
A)True
B)False
Q5) The simplest form of addressing is __________ addressing.
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Chapter 14: Processor Structure and Function
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Q1) The allocation of control information between registers and memory are not considered to be a key design issue.
A)True
B)False
Q2) The ARM architecture supports _______ execution modes.
A)2
B)8
C)11
D)7
Q3) _________ registers enable the machine or assembly language programmer to minimize main memory references by optimizing use of registers.
Q4) The major components of the processor are an arithmetic and logic unit (ALU)and a __________.
Q5) A __________ occurs when the pipeline,or some portion of the pipeline,must stall because conditions do not permit continued execution.
Q6) __________ or fetch overlap is where,while the second stage is executing the instruction,the first stage takes advantage of any unused memory cycles to fetch and buffer the next instruction.
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Chapter 15: Reduced Instruction Set Computers
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Q1) Blocks of memory,recently used global variables,memory addressing,and one operand addressed and accessed per cycle are characteristics of _________ organizations.
Q2) Individual variables,compiler assigned global variables,register addressing,and multiple operands addressed and accessed in one cycle are characteristics of __________ organizations.
Q3) Procedure calls and returns are not important aspects of HLL programs.
A)True
B)False
Q4) The work that has been done on assessing merits of the RISC approach can be grouped into two categories: quantitative and _________.
Q5) RISC processors are more responsive to interrupts because interrupts are checked between rather elementary operations.
A)True
B)False
Q6) A ________ architecture replicates each of the pipeline stages so that two or more instructions at the same stage of the pipeline can be processed simultaneously.
Q7) The acronym RISC stands for __________.
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Chapter 16: Parallelism and Superscalar Processors
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Q1) __________ exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping.
A)Flow dependency
B)Instruction-level parallelism
C)Machine parallelism
D)Instruction issue
Q2) Which of the following is a hardware technique that can be used in a superscalar processor to enhance performance?
A)duplication of resources
B)out-of-order issue
C)renaming
D)all of the above
Q3) Resources include: memories,caches,buses,and register-file ports.
A)True
B)False
Q4) The _________ predicts the instruction stream,fetches instructions from the L1 instruction cache,and places the fetched instructions into a buffer for consumption by the decode pipeline.
Q5) An alternative to _________ is a scoreboarding.
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Chapter 17: Parallel Processing
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Q1) With multithreading the instruction stream is divided into several smaller streams,known as threads,such that the threads can be executed in parallel.
A)True
B)False
Q2) ______ protocols distribute the responsibility for maintaining cache coherence among all of the cache controllers in a multiprocessor.
Q3) Which of the following is an essential characteristic of cloud computing?
A)rapid elasticity
B)measured service
C)broad network access
D)all of the above
Q4) The main drawback of the bus organization is reliability.
A)True
B)False
Q5) Symmetric multiprocessors (SMPs)are one of the earliest,and still the most common,example of parallel organization.
A)True
B)False
Q6) The four states of the MESI protocol are: modified,shared,invalid,and ______.
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Chapter 18: Multicore Computers
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Q1) ___________ states that performance increase is roughly proportional to square root of increase in complexity.
A)Pollack's Rule
B)Moore's Law
C)Amdahl's Law
D)MOESI Rule
Q2) _________ is when multiple pipelines are constructed by replicating execution resources,enabling parallel execution of instructions in parallel pipelines so long as hazards are avoided.
A)Vectoring
B)Superscalar
C)Hybrid multithreading
D)Pipelining
Q3) The SCU uses hybrid MESI and _________ protocols to maintain coherency between the individual L1 data caches and the L2 cache.
Q4) The most prominent trend in terms of heterogeneous multicore design is the use of both CPUs and __________ on the same chip.
Q5) The principal building block of the IBM zEnterprise EC12 mainframe is the
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Chapter 19: General-Purpose Graphic Processing Units
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Q1) CUDA C is a C / C++ based language.
A)True
B)False
Q2) The fundamental building block of the Gen8 architecture is the ________ unit.
Q3) The GPU is most efficient when it is processing as many warps as possible to keep the CUDA cores maximally utilized.
A)True
B)False
Q4) A kernel typically will have few to no branching statements.
A)True
B)False
Q5) The __________ is designed specifically to be optimized for fast three-dimensional (3D)graphics rendering and video processing.
A)CPU
B)GPU
C)CU
D)ALU
Q6) The _________ scheduler breaks up each thread block it is processing into warps.
Q7) A _________ is a single instance of the kernel function.
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Chapter 20: Control Unit Operation
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Q1) The six things needed to specify the function of a processor are: operations (opcodes),addressing modes,registers,I / O module interface,memory module interface,and ________.
Q2) The ________ portion of the control unit issues a repetitive sequence of pulses.
A)instruction register
B)flag
C)control bus signals
D)clock
Q3) One technique for implementing a control unit is referred to as hardwired implementation,in which the control unit is essentially a state machine circuit.
A)True
B)False
Q4) The sequence of instruction cycles are always the same as the written sequence of instructions that make up the program.
A)True
B)False
Q5) The ____________ generated by the control unit cause the opening and closing of logic gates,resulting in the transfer of data to and from registers and the operation of the ALU.
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Chapter 21: Microprogrammed Control
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Q1) An alternative,which has been used in many CISC processors,is to implement a __________ control unit.
Q2) The principal advantage of the use of microprogramming to implement a control unit is that it simplifies the design of the control unit.
A)True
B)False
Q3) The advantage of horizontal microinstructions is that they are more compact than vertical microinstructions,at the expense of a small additional amount of logic and time delay.
A)True
B)False
Q4) The TI 8800 Software Development Board is a microprogrammable 32-bit computer card.
A)True
B)False
Q5) A ________________ instruction depends on the following types of information: ALU flags,part of the opcode or address mode fields of the machine instruction; parts of a selected register -- such as the sign bit,and status bits within the control unit.
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