Digital Systems Design
Final Exam
Course Introduction
Digital Systems Design explores the fundamental concepts and practical methodologies for designing and analyzing digital electronic systems. This course covers binary number systems, Boolean algebra, combinational and sequential logic, and the use of hardware description languages such as VHDL or Verilog. Students will learn to model, simulate, and implement digital circuits, ranging from simple logic gates to complex programmable devices like FPGAs. Through theoretical lectures and hands-on projects, the course bridges the gap between digital logic theory and real-world hardware design, preparing students for advanced studies or careers in electronics, computer engineering, and embedded system development.
Recommended Textbook
Computer Organization and Architecture 10th Edition by William Stallings
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Chapter 1: Basic Concepts and Computer Evolution
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Q1) The _________ stores data.
A)system bus
B)I / O
C)main memory
D)control unit
Answer: C
Q2) _________ attributes include hardware details transparent to the programmer.
A)Interface
B)Organizational
C)Memory
D)Architectural
Answer: B
Q3) When data are moved over longer distances,to or from a remote device,the process is known as __________.
A)data communications
B)registering
C)structuring
D)data transport
Answer: A
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Chapter 2: Performance Issues
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Q1) ___________ is the ability to issue more than one instruction in every processor clock cycle.
Answer: Superscalar execution
Q2) Cloud service providers use massive high-performance banks of servers to satisfy high-volume,high-transaction-rate applications for a broad spectrum of clients.
A)True
B)False
Answer: True
Q3) Year by year the cost of computer systems continues to rise.
A)True
B)False
Answer: False
Q4) At the most fundamental level,the speed of a processor is dictated by the pulse frequency produced by the clock,measured in cycles per second,or _________.
Answer: Hertz (Hz)
Q5) The __________ Mean gives consistent results regardless of which system is used as a reference.
Answer: Geometric
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Chapter 3: A Top-Level View of Computer Function and
Interconnection
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Q1) It is not possible to connect I / O controllers directly onto the system bus.
A)True
B)False
Answer: False
Q2) The __________ is a popular high-bandwidth,processor-independent bus that can function as a mezzanine or peripheral bus.
Answer: peripheral component interconnect (PCI)
Q3) The most common classes of interrupts are: program,timer,I / O and ________.
Answer: hardware failure
Q4) A bus that connects major computer components (processor,memory,I / O)is called a __________.
A)system bus
B)address bus
C)data bus
D)control bus
Answer: A
Q5) Interrupts do not improve processing efficiency.
A)True
B)False
Answer: False
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Chapter 4: Cache Memory
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Q1) The L1 cache is slower than the L3 cache.
A)True
B)False
Q2) individual blocks or records have a unique address based on physical location with __________.
A)associative access
B)physical access
C)direct access
D)sequential access
Q3) The most commonly used physical types of memory are: semiconductor memory,__________ memory (used for disk and tape),and optical and magneto-optical.
Q4) The Pentium 4 _________ component executes micro-operations,fetching the required data from the L1 data cache and temporarily storing results in registers.
A)fetch / decode unit
B)out-of-order execution logic
C)execution unit
D)memory subsystem
Q5) __________ memory consists of peripheral storage devices,such as disk and tape.
Q6) One byte equals __________ bits.
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Chapter 5: Internal Memory
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Q1) __________ increases the data transfer rate by increasing the operational frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip.
A)DDR2
B)RDRAM
C)CDRAM
D)DDR3
Q2) A __________ RAM is a digital device that uses the same logic elements used in the processor.
Q3) A __________ contains a permanent pattern of data that cannot be changed,is nonvolatile,and cannot have new data written into it.
A)RAM
B)SRAM
C)ROM
D)flash memory
Q4) A DDR3 module transfers data at a clock rate of __________ Mbps.
A)600 to 1200
B)800 to 2133
C)1000 to 2000
D)1500 to 3000
Page 7
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Chapter 6: External Memory
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Q1) Flash memory becomes unusable after a certain number of writes.
A)True
B)False
Q2) The SSDs now on the market use a type of semiconductor memory referred to as flash memory.
A)True
B)False
Q3) __________ heads are used in sealed drive assemblies that are almost free of contaminants and the head is actually an aerodynamic foil that rests lightly on the platter's surface when the disk is motionless.
Q4) When the magnetizable coating is applied to both sides of the platter the disk is then referred to as _________.
A)multiple sided
B)substrate
C)double sided
D)all of the above
Q5) A _________ drive is a memory device made with solid-state components that can be used as a replacement to a hard disk drive.
Q6) Data is organized on the platter in a concentric set of rings called ________.
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Chapter 7: Input Output
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Q1) A ________ controls multiple high-speed devices and,at any one time,is dedicated to the transfer of data with one of those devices.
Q2) An I / O module that takes on most of the detailed processing burden,presenting a high-level interface to the processor,is usually referred to as an _________.
A)I / O channel
B)I / O command
C)I / O controller
D)device controller
Q3) It is the responsibility of the processor to periodically check the status of the I / O module until it finds that the operation is complete.
A)True
B)False
Q4) A set of I / O modules is a key element of a computer system.
A)True
B)False
Q5) An external device connected to an I / O module is often referred to as a __________ device.
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Chapter 8: Operating System Support
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Q1) ________ is when the processor spends most of its time swapping pages rather than executing instructions.
A)Swapping
B)Thrashing
C)Paging
D)Multitasking
Q2) ARM provides a versatile virtual memory system architecture that can be tailored to the needs of the embedded system designer.
A)True
B)False
Q3) The ________ scheduler is also known as the dispatcher.
A)long-term
B)medium-term
C)short-term
D)I / O
Q4) Managers are users of domains that must observe the access permissions of the individual sections and / or pages that make up that domain.
A)True
B)False
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Chapter 9: Number Systems
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Q1) Hexadecimal notation is only used for representing integers.
A)True
B)False
Q2) The binary string 110111100001 is equivalent to __________.
A)DE1<sub>16</sub>
B)C78<sub>16</sub>
C)FF64<sub>16</sub>
D)B8F<sub>16</sub>
Q3) The decimal system has a base of _________.
A)0
B)10
C)100
D)1000
Q4) Negative powers of 10 are used to represent the positions of the numbers for decimal fractions.
A)True
B)False
Q5) A nibble is a grouping of four decimal digits.
A)True
B)False
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Chapter 10: Computer Arithmetic
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Q1) The register contains additional bits,called __________,which are used to pad out the right end of the significand with 0s.
Q2) Positive numbers less than 2-127 are called ________.
A)positive underflow
B)positive overflow
C)negative underflow
D)negative overflow
Q3) Negative numbers less than -(2 - 2-23)x 2 128 are called _________.
A)positive underflow
B)positive overflow
C)negative underflow
D)negative overflow
Q4) _________ occurs when an arithmetic operation results in an absolute value greater than can be expressed with an exponent of 128.
Q5) One of the trade-offs of floating-point math is that many calculations produce results that are not exact and have to be rounded to the nearest value that the notation can represent.
A)True
B)False
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Chapter 11: Digital Logic
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Q1) The unary operation _________ inverts the value of its operand.
A)OR
B)NOT
C)NAND
D)XOR
Q2) A ________ is an interconnected set of gates whose output at any time is a function only of the input at that time.
Q3) The value to be loaded into the program counter can come from a binary counter,the instruction register,or the output of the ALU.
A)True
B)False
Q4) A _________ accepts and / or transfers information serially.
A)S-R latch
B)shift register
C)FPGA
D)parallel register
Q5) The _________ connects multiple inputs to a single output.
Q6) Each gate is defined in three ways: graphic symbol,algebraic notation,and
Page 13
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Chapter 12: Characteristics and Functions
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Q1) Most machines provide the basic arithmetic operations of add, subtract,multiply,and divide.
A)True
B)False
Q2) The _________ instruction includes an implied address.
A)skip
B)rotate
C)stack
D)push
Q3) Intel's ________ technology is a set of highly optimized instructions for multimedia tasks.
Q4) ARM processors support data types of 8 (byte),16 (halfword), and 32 (word)bits in length.
A)True
B)False
Q5) The focus of MMX technology is multimedia programming.
A)True
B)False
Q6) A self-contained computer program that is incorporated into a larger program is a
Page 14
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Chapter 13: Addressing Modes and Formats
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Q1) The method of calculating the EA is the same for both base-register addressing and indexing.
A)True
B)False
Q2) The only form of addressing for branch instructions is _________ addressing.
A)register
B)relative
C)base
D)immediate
Q3) For the _________ mode,the operand is included in the instruction.
A)immediate
B)base
C)register
D)displacement
Q4) One advantage of linking the addressing mode to the operand rather than the opcode is that any addressing mode can be used with any opcode.
A)True
B)False
Q5) The simplest form of addressing is __________ addressing.
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Chapter 14: Processor Structure and Function
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Q1) The three types of data hazards are: read after write (RAW),write after write (WAW),and _________.
Q2) The allocation of control information between registers and memory are not considered to be a key design issue.
A)True
B)False
Q3) The _________ element is needed to transfer data between the various registers and the ALU.
Q4) A ________ hazard occurs when there is a conflict in the access of an operand location.
A)resource
B)data
C)structural
D)control
Q5) Instruction pipelining is a powerful technique for enhancing performance but requires careful design to achieve optimum results with reasonable complexity.
A)True
B)False
Q6) An instruction cycle includes the following stages: fetch,execute,and _______.
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Chapter 15: Reduced Instruction Set Computers
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Q1) Although a variety of different approaches to reduced instruction set architecture have been taken,certain characteristics are common to all of them: register-to-register operations,simple addressing modes,simple instruction formats,and __________.
Q2) The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage.
A)write back
B)tag check
C)data cache
D)instruction execute
Q3) _________ is the fastest available storage device.
A)Main memory
B)Cache
C)Register storage
D)HLL
Q4) Which stage is required for load and store operations?
A)I
B)E
C)D
D)all of the above
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Chapter 16: Parallelism and Superscalar Processors
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Q1) The term ________ refers to a machine that is designed to improve the performance of the execution of scalar instructions.
Q2) Superscalar instruction issue policies are grouped into the following categories: in-order issue with in-order completion,out-of-order issue with out-of-order completion,and ____________.
Q3) The instructions following a branch have a _________ on the branch and cannot be executed until the branch is executed.
A)resource dependency
B)procedural dependency
C)output dependency
D)true data dependency
Q4) The term _________ parallelism refers to the degree to which,on average,the instructions of a program can be executed in parallel.
Q5) The ________ is a buffer used to decouple the decode and execute stages of the pipeline to allow out-of-order issue.
Q6) A ________ implementation of a processor architecture is one in which common instructions can be initiated simultaneously and executed independently.
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Chapter 17: Parallel Processing
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Q1) The objective with NUMA is to maintain a transparent system wide memory while permitting multiple multiprocessor nodes, each with its own bus or other internal interconnect system.
A)True
B)False
Q2) Which of the following is an essential characteristic of cloud computing?
A)rapid elasticity
B)measured service
C)broad network access
D)all of the above
Q3) Computer systems that fall into the ________ category have a set of processors that simultaneously execute different instruction sequences on different data sets.
Q4) The __________ is the simplest mechanism for constructing a multiprocessor system.
Q5) An SMP operating system manages processor and other computer resources so that the user perceives a single operating system controlling system resources.
A)True
B)False
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Chapter 18: Multicore Computers
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Q1) A potential advantage to having only dedicate L2 caches on the chip is that each core enjoys more rapid access to its private L2 cache.
A)True B)False
Q2) An advantage of using a shared L2 cache on the chip is that data shared by multiple cores is not replicated at the shared cache level.
A)True B)False
Q3) ________ is a multithreaded process that provides scheduling and memory management for Java applications.
Q4) The potential performance benefits of a multicore organization depend on the ability to effectively exploit the parallel resources available to the application. A)True B)False
Q5) The principal building block of the IBM zEnterprise EC12 mainframe is the
Q6) _________ applications are characterized by the presence of many single-threaded processes.
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Chapter 19: General-Purpose Graphic Processing Units
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Q1) The first NVIDIA GPU with added GPGPU support hardware was the _________ .
Q2) An instance of the kernel on the GPU is a ___________ .
A)thread
B)warp
C)grid
D)block
Q3) Because the GPU and the CPU are designed and optimized for two significantly different types of applications,their architectures differ significantly.
A)True
B)False
Q4) In 2006 NVIDIA facilitated the use of its new GPGPU language,________ .
A)GPU / GP
B)SIMD
C)CUDA
D)NVIDIA C
Q5) A __________ program can be divided into three general sections: code to be run on the device,code to be run on the host,and the code related to the transfer of data between the host and the device.
Q6) The fundamental building block of the Gen8 architecture is the ________ unit.
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Chapter 20: Control Unit Operation
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Q1) __________ are the functional,or atomic,operations of a processor.
A)Micro-operations
B)Interrupts
C)Subcycles
D)All of the above
Q2) The control unit is the engine that runs the entire computer.
A)True
B)False
Q3) One technique for implementing a control unit is referred to as hardwired implementation,in which the control unit is essentially a state machine circuit.
A)True
B)False
Q4) The _____________ must control the state of the instruction cycle.
Q5) Each phase of the instruction cycle can be decomposed into a sequence of elementary micro-operations.
A)True
B)False
Q6) __________ is when the control unit examines the opcode and generates a sequence of micro-operations based on the value of the opcode.
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Chapter 21: Microprogrammed Control
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Q1) In executing a microprogram the address of the next microinstruction to be executed is in which of the following categories?
A)determined by instruction register
B)branch
C)next sequential address
D)all of the above
Q2) It is easier to design in hardware than in firmware.
A)True
B)False
Q3) A microprogram is midway between hardware and software. A)True
B)False
Q4) _________ processors,with their simpler instruction format,typically use hardwired control units.
Q5) The control unit design is very flexible. A)True
B)False
Q6) Two approaches can be taken to organizing the encoded microinstruction into fields: functional and __________.
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