Digital Logic Design
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Course Introduction
Digital Logic Design introduces the fundamental concepts and principles of digital systems, focusing on the analysis and design of combinational and sequential circuits. The course covers topics such as binary number systems, Boolean algebra, logic gates, minimization techniques, flip-flops, registers, counters, and memory devices. Students will learn how to interpret and construct truth tables, use Karnaugh maps for circuit simplification, and design basic digital components using hardware description languages. By the end of the course, students will be able to design and implement digital circuits used in computers and embedded systems, providing a strong foundation for further studies in computer engineering and electronics.
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Computer Organization and Architecture 10th Edition by William Stallings
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2
Chapter 1: Basic Concepts and Computer Evolution
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Q1) An I / O device is referred to as a __________.
A)CPU
B)control device
C)peripheral
D)register
Answer: C
Q2) When data are received from or delivered to a device that is directly connected to the computer,the process is known as __________.
Answer: input / output (I / O)
Q3) The hierarchical nature of complex systems is essential to both their design and their description.
A)True
B)False
Answer: True
Q4) The basic functions that a computer can perform are: data processing,data movement,control,and _________.
Answer: data storage
Q5) The __________ architecture is the architecture of IBM's mainframe product line. Answer: System / 370
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Chapter 2: Performance Issues
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Q1) The __________ measures the ability of a computer to complete a single task.
A)clock speed
B)speed metric
C)execute cycle
D)cycle time
Answer: B
Q2) The raw speed of the microprocessor will not achieve its potential unless it is fed a constant stream of work to do in the form of computer instructions.
A)True
B)False
Answer: True
Q3) An increase in clock rate means that individual operations are executed _____.
A)the same
B)slower
C)with very little change
D)more rapidly
Answer: D
Q4) __________ Law applies to a queuing system.
Answer: Little's
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Chapter 3: A Top-Level View of Computer Function and
Interconnection
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Q1) Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies,Princeton.
A)John Maulchy
B)John von Neumann
C)Herman Hollerith
D)John Eckert
Answer: B
Q2) Program execution consists of repeating the process of instruction fetch and instruction execution.
A)True
B)False
Answer: True
Q3) An I / O module cannot exchange data directly with the processor.
A)True
B)False
Answer: False
Q4) A _________ register contains the data to be written into memory or receives the data read from memory.
Answer: memory buffer (MBR)
Page 5
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Chapter 4: Cache Memory
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Q1) For set-associative mapping the cache control logic interprets a memory address as three fields: Set,Word,and __________.
Q2) A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________.
A)disk cache
B)latency
C)virtual address
D)miss
Q3) The __________ units execute micro-operations,fetching the required data from the L1 data cache and temporarily storing results in registers.
Q4) The unit of transfer must equal a word or an addressable unit.
A)True
B)False
Q5) __________ memory is a facility that allows programs to address memory from a logical point of view,without regard to the amount of main memory physically available.
Q6) The ________ rate is the rate at which data can be transferred into or out of a memory unit.
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Page 6
Chapter 5: Internal Memory
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Q1) Nonvolatile means that power must be continuously supplied to the memory to preserve the bit values.
A)True
B)False
Q2) The advantage of RAM is that the data or program is permanently in main memory and need never be loaded from a secondary storage device.
A)True
B)False
Q3) ___________ is a new type of Magnetic RAM,which features non-volatility,fast writing / reading speed,and high programming endurance and zero standby power.
Q4) __________ increases the data transfer rate by increasing the operational frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip.
A)DDR2
B)RDRAM
C)CDRAM
D)DDR3
Q5) Three common forms of read-mostly memory are: EPROM,EEPROM,and _________.
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Chapter 6: External Memory
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Q1) A removable disk can be removed and replaced with another disk.
A)True
B)False
Q2) The typical recording technique used in serial tapes is referred to as _________ recording.
Q3) A _________ drive is a memory device made with solid-state components that can be used as a replacement to a hard disk drive.
Q4) A __________ is a circular platter constructed of nonmagnetic material,called the substrate,coated with a magnetizable material.
Q5) When the magnetizable coating is applied to both sides of the platter the disk is then referred to as _________.
A)multiple sided
B)substrate
C)double sided
D)all of the above
Q6) Data are recorded on and later retrieved from the disk via a conducting coil named the _________.
Q7) Data is organized on the platter in a concentric set of rings called ________.
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Q8) The time required to move the disk arm to the required track is the __________.
Chapter 7: Input Output
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Q1) An external device connected to an I / O module is often referred to as a __________ device.
Q2) The most recent,and fastest,peripheral connection technology to become available for general-purpose use is __________,developed by Intel with collaboration from Apple.
Q3) The U.S.national version of the International Reference Alphabet is referred to as __________.
Q4) Bus arbitration makes use of vectored interrupts.
A)True B)False
Q5) A ________ controls multiple high-speed devices and,at any one time,is dedicated to the transfer of data with one of those devices.
Q6) The ________ is a single-chip,general-purpose I / O module designed for use with the Intel 80386 processor.
Q7) A multipoint external interface provides a dedicated line between the I / O module and the external device.
A)True B)False
9
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Chapter 8: Operating System Support
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Q1) _________ paging means that each page of a process is brought in only when it is needed.
Q2) Early computer systems presented two main problems: setup time and _____.
Q3) A _________ is an actual location in main memory.
A)logical address
B)partition address
C)base address
D)physical address
Q4) The ________ gives a program access to the hardware resources and services available in a system through the user instruction set architecture supplemented with high-level language library calls.
A)JCL
B)ISA
C)ABI
D)API
Q5) Uniprogramming is the central theme of modern operating systems.
A)True
B)False
Q6) __________ allows the programmer to view memory as consisting of multiple address spaces or segments.
Page 10
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Chapter 9: Number Systems
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Q1) The decimal system has a base of _________.
A)0
B)10
C)100
D)1000
Q2) Another term for "base" is __________.
A)radix
B)integer
C)position
D)digit
Q3) In any number,the leftmost digit is referred to as the __________ digit because it carries the highest value.
Q4) The _________ system has only two digits,0 and 1.
Q5) In the number 3109,the 3 is referred to as the _________.
A)most significant digit
B)least significant digit
C)radix
D)base
Q6) Binary digits grouped into sets of four bits are called a _________.
Q7) The rightmost digit is called the _________ digit.
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Chapter 10: Computer Arithmetic
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Q1) Compared with addition and subtraction,multiplication is a complex operation,whether performed in hardware of software.
A)True
B)False
Q2) The most common scheme in implementing the integer portion of the ALU is:
A)sign-magnitude representation
B)biased representation
C)twos complement representation
D)ones complement representation
Q3) For base 2 representation,a normal number is one in which the most significant bit of the significand is zero.
A)True
B)False
Q4) __________ is when the result is put back into the floating-point format and the extra bits must be eliminated in such a way as to produce a result that is close to the exact result.
Q5) __________ format is a fully specified,fixed-length binary encoding that allows data interchange between different platforms and that can be used for storage.
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Chapter 11: Digital Logic
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Q1) "Don't care" conditions are when certain combinations of values of variables never occur,and therefore the corresponding output never occurs.
A)True
B)False
Q2) A ________ is a register whose value is easily incremented by 1 modulo the capacity of the register.
Q3) The _________ table provides the value of the next output when the inputs and the present output are known,which is exactly the information needed to design the counter or any sequential circuit.
A)excitation
B)Kenough
C)J-K flip-flop
D)FPGA
Q4) In the absence of parentheses,the AND operation takes precedence over the OR operation.
A)True
B)False
Q5) A combinational circuit can be defined by Boolean equations,truth table,and
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Chapter 12: Characteristics and Functions
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Q1) A branch can be either forward or backward.
A)True
B)False
Q2) Memory references are faster than register references.
A)True
B)False
Q3) _________ instructions provide computational capabilities for processing number data.
A)Boolean
B)Logic
C)Memory
D)Arithmetic
Q4) One boundary where the computer designer and the computer programmer can view the same machine is the machine instruction set.
A)True
B)False
Q5) Opcodes are represented by abbreviations,called __________ that indicate the operation.
Q6) Intel's ________ technology is a set of highly optimized instructions for multimedia tasks.
Page 14
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Chapter 13: Addressing Modes and Formats
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Q1) Register indirect addressing uses the same number of memory references as indirect addressing.
A)True
B)False
Q2) Sometimes referred to as a pushdown list or last-in-first-out queue,a __________ is a linear array of locations.
Q3) Just as register addressing is analogous to direct addressing,________ addressing is analogous to indirect addressing.
Q4) Not common on contemporary architectures,___________ requires only one memory reference and no special calculation,but provides only a limited address space.
Q5) __________ is a design principle employed in designing the PDP-10 instruction set.
A)Orthogonality
B)Completeness
C)Direct addressing
D)All of the above
Q6) In the __________ mode the instruction includes a displacement to be added to a base register,which may be any of the general-purpose registers.
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Chapter 14: Processor Structure and Function
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Q1) The OS usually runs in ________.
A)supervisor mode
B)abort mode
C)undefined mode
D)fast interrupt mode
Q2) Two classes of events cause the x86 to suspend execution of the current instruction stream and respond to the event: interrupts and ________.
Q3) While the processor is in user mode the program being executed is unable to access protected system resources or to change mode,other than by causing an exception to occur.
A)True
B)False
Q4) Instruction pipelining is a powerful technique for enhancing performance but requires careful design to achieve optimum results with reasonable complexity.
A)True
B)False
Q5) An instruction cycle includes the following stages: fetch,execute,and _______.
Q6) Data are exchanged with the processor from external memory through a
Page 16
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Chapter 15: Reduced Instruction Set Computers
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Q1) The difference between the operations provided in high-level languages (HLLs)and those provided in computer architecture is known as the ________.
Q2) The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage.
A)write back
B)tag check
C)data cache
D)instruction execute
Q3) Blocks of memory,recently used global variables,memory addressing,and one operand addressed and accessed per cycle are characteristics of _________ organizations.
Q4) The R4000 can have as many as _______ instructions in the pipeline at the same time.
A)8
B)10
C)5
D)3
Q5) The acronym CISC stands for _________.
Q6) The acronym RISC stands for __________.
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Chapter 16: Parallelism and Superscalar Processors
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Q1) The reorder buffer is temporary storage for results completed out of order that are then committed to the register file in program order.
A)True
B)False
Q2) Which of the following is a fundamental limitation to parallelism with which the system must cope?
A)procedural dependency
B)resource conflicts
C)antidependency
D)all of the above
Q3) Resources include: memories,caches,buses,and register-file ports.
A)True
B)False
Q4) ________ refers to the process of initiating instruction execution in the processor's functional units.
A)Instruction issue
B)In-order issue
C)Out-of-order issue
D)Procedural issue
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Chapter 17: Parallel Processing
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Q1) With multithreading the instruction stream is divided into several smaller streams,known as threads,such that the threads can be executed in parallel.
A)True
B)False
Q2) A _________ problem arises when multiple copies of the same data can exist in different caches simultaneously,and if processors are allowed to update their own copies freely,an inconsistent view of memory can result.
A)cache coherence
B)cluster
C)failover
D)failback
Q3) The term SMP refers to a computer hardware architecture and also to the operating system behavior that reflects that architecture.
A)True
B)False
Q4) An approach that allows for a high degree of instruction-level parallelism without increasing circuit complexity or power consumption is called ________.
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Chapter 18: Multicore Computers
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Q1) An advantage of using a shared L2 cache on the chip is that data shared by multiple cores is not replicated at the shared cache level.
A)True B)False
Q2) A potential advantage to having only dedicate L2 caches on the chip is that each core enjoys more rapid access to its private L2 cache.
A)True B)False
Q3) A single piece of silicon is called a ________.
Q4) The organizational changes in processor design have primarily been focused on increasing instruction-level parallelism so that more work could be done in each clock cycle.
A)True B)False
Q5) The ARM11 MPCore is an example of the L1 cache being divided into instruction and data caches.
A)True B)False
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Chapter 19: General-Purpose Graphic Processing Units
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Q1) CUDA C is a C / C++ based language.
A)True
B)False
Q2) The GPU is most efficient when it is processing as many warps as possible to keep the CUDA cores maximally utilized.
A)True
B)False
Q3) The dual warp scheduler will break up each thread block it is processing into
A)kernels
B)warps
C)grids
D)all of the above
Q4) To enhance performance,a technique known as __________ is used for the shared L3 data cache.
A)cache banking
B)thread blocking
C)streaming
D)warping
Q5) The _________ GPU has a total of 16 SMs x 32 CUDA cores / SM,or 512 CUDA cores.
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Chapter 20: Control Unit Operation
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Q1) The _________ cycle occurs at the beginning of each instruction cycle and causes an instruction to be fetched from memory.
A)execute
B)indirect
C)fetch
D)interrupt
Q2) The groupings of micro-operations must follow which rule?
A)a sequence of events does not need to be followed
B)use read to and write from the same register in one time unit
C)conflicts must be avoided
D)all of the above
Q3) The execution of a program consists of the sequential execution of instructions.
A)True
B)False
Q4) Which of the following is an Intel 8085 external signal?
A)CLK(OUT)
B)read control
C)HOLDA
D)all of the above
Q5) The _____________ must control the state of the instruction cycle.
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Chapter 21: Microprogrammed Control
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Q1) To implement a control unit as an interconnection of basic logic elements is a very simple task.
A)True
B)False
Q2) In executing a microprogram the address of the next microinstruction to be executed is in which of the following categories?
A)determined by instruction register
B)branch
C)next sequential address
D)all of the above
Q3) The PDP-11 is the first member of the LSI-11 family that was offered as a single board processor.
A)True
B)False
Q4) The TI 8800 Software Development Board is a microprogrammable 32-bit computer card.
A)True
B)False
Q5) The LSI-11 is a good example of a __________ microinstruction approach.
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