

Computer Organization
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Course Introduction
Computer Organization explores the fundamental components and operational principles of modern computer systems, focusing on the internal structure and function of digital computers. The course covers topics such as data representation, digital logic, processor architecture, instruction sets, memory hierarchy, input/output systems, and assembly language programming. Through a combination of theoretical concepts and practical exercises, students gain an understanding of how hardware and software interact at the machine level, enabling them to analyze system performance and design more efficient, reliable computer architectures.
Recommended Textbook
Computer Organization and Architecture 10th Edition by William Stallings
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Chapter 1: Basic Concepts and Computer Evolution
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Q1) Both the structure and functioning of a computer are,in essence, simple.
A)True
B)False
Answer: True
Q2) The _________ controls the operation of the CPU and hence the computer.
Answer: control unit
Q3) Changes in computer technology are finally slowing down.
A)True
B)False
Answer: False
Q4) _________ refers to the operational units and their interconnections that realize the architectural specifications.
Answer: Computer organization
Q5) The major structural components of the CPU are: control unit,register,CPU interconnection,and __________.
Answer: arithmetic and logic unit (ALU)
Q6) _________ is the way in which the components are interrelated.
Answer: Structure
Q7) The __________ architecture is the architecture of IBM's mainframe product line. Answer: System / 370
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Chapter 2: Performance Issues
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Q1) The use of multiple processors on the same chip is referred to as __________ and provides the potential to increase performance without increasing the clock rate.
A)multicore
B)GPU
C)data channels
D)MPC
Answer: A
Q2) A straight comparison of clock speeds on different processors tells the whole story about performance.
A)True
B)False
Answer: False
Q3) The __________ measures the ability of a computer to complete a single task.
A)clock speed
B)speed metric
C)execute cycle
D)cycle time
Answer: B
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Chapter 3: A Top-Level View of Computer Function and Interconnection
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Q1) The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer.
A)transaction layer
B)root layer
C)configuration layer
D)transport layer
Answer: A
Q2) Interrupts do not improve processing efficiency.
A)True
B)False
Answer: False
Q3) A(n)_________ is generated by some condition that occurs as a result of an instruction execution.
A)timer interrupt
B)I / O interrupt
C)program interrupt
D)hardware failure interrupt
Answer: C
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Chapter 4: Cache Memory
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Q1) A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________.
A)disk cache
B)latency
C)virtual address
D)miss
Q2) The Pentium 4 _________ component executes micro-operations,fetching the required data from the L1 data cache and temporarily storing results in registers.
A)fetch / decode unit
B)out-of-order execution logic
C)execution unit
D)memory subsystem
Q3) The unit of transfer must equal a word or an addressable unit.
A)True
B)False
Q4) The cache consists of blocks called __________.
Q5) It has become possible to have a cache on the same chip as the processor.
A)True
B)False
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Chapter 5: Internal Memory
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Q1) RAM must be provided with a constant power supply.
A)True
B)False
Q2) ___________ is a new type of Magnetic RAM,which features non-volatility,fast writing / reading speed,and high programming endurance and zero standby power.
Q3) Nonvolatile means that power must be continuously supplied to the memory to preserve the bit values.
A)True
B)False
Q4) The simplest of the error-correcting codes is the _________ code.
Q5) A static RAM will hold its data as long as power is supplied to it.
A)True
B)False
Q6) Three common forms of read-mostly memory are: EPROM,EEPROM,and _________.
Q7) Which of the following memory types are nonvolatile?
A)erasable PROM
B)programmable ROM
C)flash memory
D)all of the above

7
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Chapter 6: External Memory
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Q1) The _________ strategy employs multiple disk drives and distributes data in such a way as to enable simultaneous access to data from multiple drives,thereby improving I / O performance and allowing easier incremental increases in capacity.
Q2) The time required to move the disk arm to the required track is the __________.
Q3) Scanning information at the same rate by rotating the disk at a fixed speed is known as the _________.
A)constant angular velocity
B)magnetoresistive
C)rotational delay
D)constant linear velocity
Q4) A __________ disk is permanently mounted in the disk drive,such as the hard disk in a personal computer.
A)nonremovable
B)movable-head
C)double sided
D)removable
Q5) RAID levels 4 through 6 make use of an __________ access technique that allows separate I / O requests to be satisfied in parallel.
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Chapter 7: Input Output
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Q1) When large volumes of data are to be moved,a more efficient technique is direct memory access (DMA).
A)True
B)False
Q2) The I / O function includes a _________ requirement to coordinate the flow of traffic between internal resources and external devices.
A)cycle
B)status reporting
C)control and timing
D)data
Q3) When the processor,main memory,and I / O share a common bus,two modes of addressing are possible: memory mapped and ________.
Q4) A ________ is used to connect storage systems,routers,and other peripheral devices to an InfiniBand switch.
A)target channel adapter
B)InfiniBand switch
C)host channel adapter
D)subnet
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Chapter 8: Operating System Support
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Q1) Swapping is an I / O operation.
A)True
B)False
Q2) The OS maintains a __________ for each process that shows the frame location for each page of the process.
A)kernel
B)page table
C)TLB
D)logical address
Q3) Three key interfaces in a typical computer system are: instruction set architecture,application programming interface,and ___________.
Q4) Scheduling and memory management are the two OS functions that are most relevant to the study of computer organization and architecture.
A)True
B)False
Q5) The _________ is a program that manages the computer's resources,provides services for programmers,and schedules the execution of other programs.
Q6) Early computer systems presented two main problems: setup time and _____.
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Chapter 9: Number Systems
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Q1) In any number,the leftmost digit is referred to as the __________ digit because it carries the highest value.
Q2) A nibble is a grouping of four decimal digits.
A)True
B)False
Q3) Although convenient for computers,the binary system is exceedingly cumbersome for human beings.
A)True
B)False
Q4) In everyday life we use a system based on decimal digits to represent numbers,and refer to the system as the __________.
Q5) In a __________ number system,each number is represented by a string of digits in which each digit position i has an associated weight ri,where r is the radix of the number system.
Q6) In the number 3109,the 3 is referred to as the _________.
A)most significant digit
B)least significant digit
C)radix
D)base
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Chapter 10: Computer Arithmetic
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Q1) If two numbers are added,and they are both positive or both negative,then _________ occurs if and only if the result has the opposite sign.
Q2) Addition and subtraction can be performed on numbers in twos complement notation by treating them as unsigned integers.
A)True
B)False
Q3) __________ means that the number is too small to be represented and it may be reported as 0.
A)Negative underflow
B)Exponent underflow
C)Positive underflow
D)Significand underflow
Q4) __________ is when a positive exponent exceeds the maximum possible exponent value.
A)Significand underflow
B)Significand overflow
C)Exponent overflow
D)Exponent underflow
Q5) The use of subnormal numbers is referred to as _________ underflow.
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Chapter 11: Digital Logic
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Sample Questions
Q1) A combinational circuit consists of n binary inputs and m binary outputs.
A)True
B)False
Q2) A ________ is a register whose value is easily incremented by 1 modulo the capacity of the register.
Q3) To ________ a signal is to cause a signal line to make a transition from its logically false (0)state to its logically true (1)state.
Q4) The unary operation _________ inverts the value of its operand.
A)OR
B)NOT
C)NAND
D)XOR
Q5) The operation of the digital computer is based on the storage and processing of binary data.
A)True
B)False
Q6) Logical functions are implemented by the interconnection of decoders.
A)True
B)False
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Chapter 12: Characteristics and Functions
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Q1) Which data type is defined in MMX?
A)packed byte
B)packed word
C)packed doubleword
D)all of the above
Q2) It has become common practice to use a symbolic representation of machine instructions.
A)True
B)False
Q3) The entire set of parameters,including return address,which is stored for a procedure invocation is referred to as a _________.
A)branch
B)stack frame
C)pop
D)push
Q4) Opcodes are represented by abbreviations,called __________ that indicate the operation.
Q5) _________ are bits in special registers that may be set by certain operations and used in conditional branch instructions.
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Chapter 13: Addressing Modes and Formats
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Q1) _________ is a principle by which two variables are independent of each other.
A)Opcode
B)Orthogonality
C)Completeness
D)Autoindexing
Q2) The __________ instruction set is designed to increase the performance of ARM implementations that use a 16-bit or narrower memory data bus and to allow better code density than provided by the ARM instruction set.
Q3) __________ has the advantage of flexibility,but the disadvantage of complexity.
A)Stack addressing
B)Displacement addressing
C)Direct addressing
D)Register addressing
Q4) Sometimes referred to as a pushdown list or last-in-first-out queue,a __________ is a linear array of locations.
Q5) __________ explicitly specifies which segment register an instruction should use,overriding the default segment-register selection generated by the x86 for that instruction.
Q6) The simplest form of addressing is __________ addressing.
Page 15
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Chapter 14: Processor Structure and Function
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Q1) The major components of the processor are an arithmetic and logic unit (ALU)and a
Q2) The three types of data hazards are: read after write (RAW),write after write (WAW),and _________.
Q3) Condition codes facilitate multiway branches.
A)True
B)False
Q4) Two classes of events cause the x86 to suspend execution of the current instruction stream and respond to the event: interrupts and ________.
Q5) _________ is a pipeline hazard.
A)Control
B)Resource
C)Data
D)All of the above
Q6) The ________ determines the opcode and the operand specifiers.
A)decode instruction
B)fetch operands
C)calculate operands
D)execute instruction
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Chapter 15: Reduced Instruction Set Computers
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Q1) _________ determines the control and pipeline organization.
A)Calculation
B)Execution sequencing
C)Operations performed
D)Operands used
Q2) The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage.
A)write back
B)tag check
C)data cache
D)instruction execute
Q3) SPARC refers to an architecture defined by ________.
A)Microsoft
B)Apple
C)Sun Microsystems
D)IBM
Q4) It is common for programs,both system and application,to continue to exhibit new bugs after years of operation.
A)True
B)False
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Chapter 16: Parallelism and Superscalar Processors
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Q1) _________ is determined by the number of instructions that can be fetched and executed at the same time and by the speed and sophistication of the mechanisms that the processor uses to find independent instructions.
A)Machine parallelism
B)Instruction-level parallelism
C)Output dependency
D)Procedural dependency
Q2) In the scalar organization there are multiple functional units,each of which is implemented as a pipeline and provides a degree of parallelism by virtue of its pipelined structure.
A)True
B)False
Q3) Committing or _________ the instruction is when instructions are conceptually put back into sequential order and their results are recorded.
Q4) The term ________ refers to a machine that is designed to improve the performance of the execution of scalar instructions.
Q5) A _________ is a competition of two or more instructions for the same resource at the same time.
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Chapter 17: Parallel Processing
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Q1) A ________ is a group of interconnected,whole computers working together as a unified computing resource that can create the illusion of being one machine.
Q2) An attractive feature of an SMP is that the existence of multiple processors is transparent to the user.
A)True
B)False
Q3) A taxonomy first introduced by _______ is still the most common way of categorizing systems with parallel processing capability.
A)Randolph
B)Flynn
C)von Neuman
D)Desai
Q4) ______ protocols distribute the responsibility for maintaining cache coherence among all of the cache controllers in a multiprocessor.
Q5) Computer systems that fall into the _________ category have a single machine instruction that controls the simultaneous execution of a number of processing elements on a lockstep basis.
Q6) Two key characteristics of a process are: scheduling / execution and ________.
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Chapter 18: Multicore Computers
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Q1) The ARM11 MPCore is an example of the L1 cache being divided into instruction and data caches.
A)True
B)False
Q2) The potential performance benefits of a multicore organization depend on the ability to effectively exploit the parallel resources available to the application.
A)True
B)False
Q3) _________ applications are characterized by the presence of many single-threaded processes.
Q4) Even if an individual application does not scale to take advantage of a large number of threads,it is still possible to gain from multicore architecture by running multiple instances of the application in parallel.
A)True
B)False
Q5) __________ applications are characterized by having a small number of highly threaded processes.
Q6) A single piece of silicon is called a ________.
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Chapter 19: General-Purpose Graphic Processing Units
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Q1) A _________ is a bundle of 32 threads that start at the same starting address and their thread IDs are consecutive.
A)warp
B)grid
C)block
D)grouping
Q2) CUDA C is a C / C++ based language.
A)True
B)False
Q3) The first NVIDIA GPU with added GPGPU support hardware was the _________ .
Q4) All but one set of GPU processor cores will be idle,while one SM is bearing the full processing load.
A)True
B)False
Q5) The total number of threads defined is typically in the thousands to maximize the utilization of the GPU processor cores as well as maximize the available speedup.
A)True
B)False
Q6) The _________ scheduler breaks up each thread block it is processing into warps.
21
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Chapter 20: Control Unit Operation
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Q1) The __________ register contains the value to be stored in memory or the last value read from memory.
Q2) The use of common data paths simplifies the interconnection layout and the control of the processor.
A)True
B)False
Q3) For the control unit to perform its function it must have inputs that allow it to determine the state of the system and outputs that allow it to control the behavior of the system.
A)True
B)False
Q4) A single micro-operation generally involves which of the following?
A)a transfer between registers
B)a transfer between a register and an external bus
C)a transfer between a register and the ALU
D)all of the above
Q5) Each micro-operation of the fetch cycle involves the movement of data into or out of a register.
A)True
B)False

22
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Chapter 21: Microprogrammed Control
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Q1) The control unit design is very flexible.
A)True
B)False
Q2) The LSI-11 is a good example of a __________ microinstruction approach.
Q3) The terms __________ relate to the relative width of microinstructions.
A)packed / unpacked
B)hard / soft
C)horizontal / vertical
D)direct / indirect
Q4) The principal function of the 8818 __________ is to generate the next microinstruction address for the microprogram.
Q5) The two basic tasks performed by a microprogrammed control unit are microinstruction sequencing and microinstruction __________.
Q6) The TI 8800 Software Development Board is a microprogrammable 32-bit computer card.
A)True
B)False
Q7) In a ________ microinstruction a code is used for each action to be performed and the decoder translates this code into individual control signals.
Page 23
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