Course Introduction
Computer Architecture Exam
Bank
Computer Architecture is the study of the design, structure, and functionality of computer systems. This course explores how computers process instructions, integrate hardware components, and manage memory and input/output operations. Topics include data representation, instruction set architectures, processor design, pipelining, cache organization, memory hierarchy, parallelism, and performance evaluation. Through theoretical analysis and practical case studies, students gain a comprehensive understanding of how computer systems are organized and how architectural decisions impact speed, efficiency, and scalability across various computing applications.
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Computer Organization and Architecture 10th Edition by William Stallings
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Page 2
Chapter 1: Basic Concepts and Computer Evolution
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Q1) When data are moved over longer distances,to or from a remote device,the process is known as __________.
A)data communications
B)registering
C)structuring
D)data transport
Answer: A
Q2) _________ is the operation of each individual component as part of the structure. Answer: Function
Q3) The hierarchical nature of complex systems is essential to both their design and their description.
A)True
B)False
Answer: True
Q4) _________ refers to the operational units and their interconnections that realize the architectural specifications.
Answer: Computer organization
Q5) __________ refers to those attributes of a system visible to a programmer. Answer: Computer architecture
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Chapter 2: Performance Issues
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Q1) A common measure of performance for a processor is the rate at which instructions are executed,expressed as millions of instructions per second (MIPS).
A)True
B)False
Answer: True
Q2) The __________ measures the ability of a computer to complete a single task.
A)clock speed
B)speed metric
C)execute cycle
D)cycle time
Answer: B
Q3) The IAS is the prototype of all subsequent general-purpose computers.
A)True
B)False
Answer: True
Q4) Processors are so inexpensive that we now have microprocessors we throw away.
A)True
B)False
Answer: True
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Chapter 3: A Top-Level View of Computer Function and
Interconnection
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Q1) A bus that connects major computer components (processor,memory,I / O)is called a __________.
A)system bus
B)address bus
C)data bus
D)control bus
Answer: A
Q2) A key requirement for PCIe is high capacity to support the needs of higher data rate I / O devices such as Gigabit Ethernet.
A)True
B)False
Answer: True
Q3) The _________ function is needed to ensure that a sending QPI entity does not overwhelm a receiving QPI entity by sending data faster than the receiver can process the data and clear buffers for more incoming data.
Answer: flow control
Q4) The QPI link layer performs two key functions: flow control and _________ control.
Answer: error
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Chapter 4: Cache Memory
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Q1) External memory is often equated with main memory.
A)True
B)False
Q2) When using the __________ technique all write operations made to main memory are made to the cache as well.
A)write back
B)LRU
C)write through
D)unified cache
Q3) The cache consists of blocks called __________.
Q4) To achieve greatest performance the memory must be able to keep up with the processor.
A)True
B)False
Q5) Both sequential access and direct access involve a shared read- write mechanism.
A)True
B)False
Q6) __________ computing deals with super computers and their software.
Q7) The three key characteristics of memory are capacity,access time,and _______.
Q8) __________ memory consists of peripheral storage devices,such as disk and tape. Page 6
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Page 7
Chapter 5: Internal Memory
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Q1) _________ can be caused by power supply problems or alpha particles.
A)Soft errors
B)AGT errors
C)Hard errors
D)SEC errors
Q2) An error-correcting code enhances the reliability of the memory at the cost of added complexity.
A)True
B)False
Q3) A typical DRAM pin configuration will include the __________ pin if necessary in order to have an even number of pins.
Q4) One distinguishing characteristic of memory that is designated as _________ is that it is possible to both read data from the memory and to write new data into the memory easily and rapidly.
A)RAM
B)ROM
C)EPROM
D)EEPROM
Q5) __________ works by creating resistance rather than directly storing charge.
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Chapter 6: External Memory
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Q1) A _________ is a high-definition video disk that can store 25 Gbytes on a single layer on a single side.
A)DVD
B)DVD-R
C)DVD-RW
D)Blu-ray DVD
Q2) A bit near the center of a rotating disk travels past a fixed point slower than a bit on the outside.
A)True
B)False
Q3) A __________ disk is permanently mounted in the disk drive,such as the hard disk in a personal computer.
A)nonremovable
B)movable-head
C)double sided
D)removable
Q4) On a movable-head system,the time it takes to position the head at the track is known as __________.
Q5) Data is organized on the platter in a concentric set of rings called ________.
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Chapter 7: Input Output
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Q1) The rotating interrupt mode allows the processor to inhibit interrupts from certain devices.
A)True
B)False
Q2) ________ is when the DMA module must force the processor to suspend operation temporarily.
A)Interrupt
B)Thunderbolt
C)Cycle stealing
D)Lock down
Q3) In a _________ interface there are multiple lines connecting the I / O module and the peripheral and multiple bits are transferred simultaneously.
Q4) There are four types of I / O commands that an I / O module may receive when it is addressed by a processor: control,test,write,and _________.
Q5) When the processor,main memory,and I / O share a common bus,two modes of addressing are possible: memory mapped and ________.
Q6) In a ________ interface there is only one line used to transmit data and bits must be transmitted one at a time.
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Chapter 8: Operating System Support
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Q1) Three key interfaces in a typical computer system are: instruction set architecture,application programming interface,and ___________.
Q2) The _________ defines the system call interface to the operating system and the hardware resources and services available in a system through the user instruction set architecture.
A)HLL
B)API
C)ABI
D)ISA
Q3) In an _________ system the user / programmer interacts directly with the computer,usually through a keyboard / display terminal to request the execution of a job or to perform a transaction.
Q4) _________ paging means that each page of a process is brought in only when it is needed.
Q5) The end user is concerned mainly with the computer's architecture.
A)True
B)False
Q6) The five defined states for a process are: new,ready,waiting,halted,and ________.
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Chapter 9: Number Systems
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Q1) It is extremely easy to convert between binary and hexadecimal notation.
A)True
B)False
Q2) In the number 3109,the 9 is referred to as the _________.
A)most significant digit
B)least significant digit
C)radix
D)base
Q3) Decimal "10" is _________ in hexadecimal.
A)1
B)A
C)0
D)FF
Q4) Although convenient for computers,the binary system is exceedingly cumbersome for human beings.
A)True
B)False
Q5) The rightmost digit is called the _________ digit.
Q6) In the _________ system,10 different digits are used to represent numbers with a base of 10.
Page 12
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Chapter 10: Computer Arithmetic
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Q1) __________ means that the number is too small to be represented and it may be reported as 0.
A)Negative underflow
B)Exponent underflow
C)Positive underflow
D)Significand underflow
Q2) Positive numbers less than 2-127 are called ________.
A)positive underflow
B)positive overflow
C)negative underflow
D)negative overflow
Q3) Actual floating-point representations include a special bit pattern to designate zero.
A)True
B)False
Q4) One of the trade-offs of floating-point math is that many calculations produce results that are not exact and have to be rounded to the nearest value that the notation can represent.
A)True
B)False
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Chapter 11: Digital Logic
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Q1) Binary addition is exactly the same as Boolean algebra.
A)True
B)False
Q2) A register is a digital circuit used within the CPU to store one or more bits of data.
A)True
B)False
Q3) The unary operation _________ inverts the value of its operand.
A)OR
B)NOT
C)NAND
D)XOR
Q4) A _________ is a combinational circuit with a number of output lines,only one of which is asserted at any time.
Q5) Each gate is defined in three ways: graphic symbol,algebraic notation,and __________.
Q6) A combinational circuit consists of n binary inputs and m binary outputs.
A)True
B)False
Q7) The simplest form of sequential circuit is the _________.
Page 14
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Chapter 12: Characteristics and Functions
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Q1) The operation of the processor is determined by the instructions it executes,referred to as _________ or computer instructions.
Q2) The focus of MMX technology is multimedia programming. A)True B)False
Q3) The __________ reference tells the processor where to fetch the next instruction after the execution of this instruction is complete.
Q4) ________ instructions are those that change the format or operate on the format of data.
Q5) The x86 provides four instructions to support procedure call / return: CALL,ENTER,LEAVE,and _________.
Q6) _________ instructions are those that can be executed only while the processor is in a certain privileged state or is executing a program in a special privileged area of memory.
Q7) The most important general categories of data are: addresses,numbers,characters,and _________.
Q8) Opcodes are represented by abbreviations,called __________ that indicate the operation.
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Chapter 13: Addressing Modes and Formats
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Q1) The advantage of __________ is that no memory reference other than the instruction fetch is required to obtain the operand.
A)direct addressing
B)immediate addressing
C)register addressing D)stack addressing
Q2) The actual mapping to a physical address is a function of the _________ and is invisible to the programmer.
Q3) For addresses that reference memory the range of addresses that can be referenced is not related to the number of address bits.
A)True
B)False
Q4) If a programmer wished to program directly in machine language it would be necessary to enter the program as ________ data.
Q5) A very powerful mode of addressing,__________ combines the capabilities of direct addressing and register indirect addressing,requiring that the instruction have two address fields,at least one of which is explicit.
Q6) The simplest form of addressing is __________ addressing.
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Chapter 14: Processor Structure and Function
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Q1) Many processor designs include a register or set of registers often known as the _________ that contain status information and condition codes.
Q2) The ________ determines the opcode and the operand specifiers.
A)decode instruction
B)fetch operands
C)calculate operands
D)execute instruction
Q3) One of the major problems in designing an instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline.
A)True
B)False
Q4) The predict-never-taken approach is the most popular of all the branch prediction methods.
A)True
B)False
Q5) Data are exchanged with the processor from external memory through a
Q6) _________ registers enable the machine or assembly language programmer to minimize main memory references by optimizing use of registers.
Page 17
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Chapter 15: Reduced Instruction Set Computers
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Q1) The Patterson study examined the dynamic behavior of _________ programs,independent of the underlying architecture.
A)HLL
B)RISC
C)CISC
D)all of the above
Q2) The major cost in the life cycle of a system is hardware.
A)True
B)False
Q3) The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage.
A)write back
B)tag check
C)data cache
D)instruction execute
Q4) The MIPS R4000 processor chip is partitioned into two sections,one containing the CPU and the other containing a _________ for memory management.
Q5) The acronym RISC stands for __________.
Q6) The acronym SPARC stands for __________.
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Chapter 16: Parallelism and Superscalar Processors
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Q1) The reorder buffer is temporary storage for results completed out of order that are then committed to the register file in program order.
A)True
B)False
Q2) The simplest instruction issue policy is to issue instructions in the exact order that would be achieved by sequential execution (in- order issue)and to write results in that same order (in-order completion).
A)True
B)False
Q3) The term ________ refers to a machine that is designed to improve the performance of the execution of scalar instructions.
Q4) ARM architecture has yet to implement superscalar techniques in the instruction pipeline.
A)True
B)False
Q5) With ____________ any number of instructions may be in the execution stage at any one time,up to the maximum degree of machine parallelism across all functional units.
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Chapter 17: Parallel Processing
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Q1) The four states of the MESI protocol are: modified,shared,invalid,and ______.
Q2) Which of the following is an essential characteristic of cloud computing?
A)rapid elasticity
B)measured service
C)broad network access
D)all of the above
Q3) With a write-update protocol there can be multiple readers but only one writer at a time.
A)True
B)False
Q4) The main drawback of the bus organization is reliability.
A)True
B)False
Q5) A __________ is an instance of a program running on a computer.
A)process
B)process switch
C)thread
D)thread switch
Q6) _________ is the easiest multithreading approach to implement.
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Q7) Two key characteristics of a process are: scheduling / execution and ________.
Chapter 18: Multicore Computers
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Q1) Database management systems and database applications are one area in which multicore systems can be used effectively.
A)True
B)False
Q2) Even if an individual application does not scale to take advantage of a large number of threads,it is still possible to gain from multicore architecture by running multiple instances of the application in parallel.
A)True
B)False
Q3) __________ applications are characterized by the presence of many single-threaded processes.
A)Java
B)Multithreaded native
C)Multi-instance
D)Multiprocess
Q4) _______ law assumes a program in which a fraction (1- f )of the execution time involves code that is inherently serial and a fraction f that involves code that is infinitely parallelizable with no scheduling overhead.
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Chapter 19: General-Purpose Graphic Processing Units
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Q1) To enhance performance,a technique known as __________ is used for the shared L3 data cache.
A)cache banking
B)thread blocking
C)streaming
D)warping
Q2) The equivalent GPU hardware component for a block is the CUDA multiprocessor (SM).
A)True
B)False
Q3) The dual warp scheduler will break up each thread block it is processing into
A)kernels
B)warps
C)grids
D)all of the above
Q4) The GPU is most efficient when it is processing as many warps as possible to keep the CUDA cores maximally utilized.
A)True
B)False
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Chapter 20: Control Unit Operation
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Q1) The number of machine cycles for an instruction depends on the number of times the processor must communicate with internal devices.
A)True
B)False
Q2) The ________ portion of the control unit issues a repetitive sequence of pulses.
A)instruction register
B)flag
C)control bus signals
D)clock
Q3) At the completion of the execute cycle a test is made to determine whether any enabled interrupts have occurred,and if they have,the interrupt cycle occurs.
A)True
B)False
Q4) The execute cycle is simple and predictable.
A)True
B)False
Q5) The control unit controls the internal flow of data.
A)True
B)False
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Chapter 21: Microprogrammed Control
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Q1) A microprogram consists of a sequence of instructions in a microprogramming language.
A)True
B)False
Q2) The PDP-11 is the first member of the LSI-11 family that was offered as a single board processor.
A)True
B)False
Q3) The terms __________ relate to the relative width of microinstructions.
A)packed / unpacked
B)hard / soft
C)horizontal / vertical
D)direct / indirect
Q4) With _________ encoding one field is used to determine the interpretation of another field.
A)resource
B)indirect
C)direct
D)functional
Q5) A sequence of instructions is known as a ___________,or firmware.
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