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Advanced Computer Architecture Chapter Exam Questions - 945 Verified Questions

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Advanced Computer Architecture

Chapter Exam Questions

Course Introduction

Advanced Computer Architecture delves into the fundamental principles and modern advancements in the design and organization of computer systems. The course covers topics such as instruction set architectures, pipelining, superscalar processing, memory hierarchies, parallelism, interconnection networks, and multiprocessor systems. Students will analyze quantitative design tradeoffs, explore emerging trends like multicore and heterogeneous architectures, and learn techniques for evaluating performance, energy efficiency, and scalability. Emphasis is placed on real-world case studies and hands-on assignments to reinforce understanding of how advanced architectures meet the demands of contemporary computing applications.

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Computer Organization and Architecture 10th Edition by William Stallings

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Chapter 1: Basic Concepts and Computer Evolution

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Q1) The major structural components of the CPU are: control unit,register,CPU interconnection,and __________.

Answer: arithmetic and logic unit (ALU)

Q2) __________ refers to those attributes of a system visible to a programmer.

Answer: Computer architecture

Q3) A __________ system is a set of interrelated subsystems.

A)secondary

B)hierarchical

C)complex

D)functional

Answer: B

Q4) The number of bits used to represent various data types is an example of an architectural attribute.

A)True

B)False

Answer: True

Q5) The basic functions that a computer can perform are: data processing,data movement,control,and _________.

Answer: data storage

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Chapter 2: Performance Issues

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Sample Questions

Q1) __________ enables the processor to keep its execution engines as busy as possible by executing instructions that are likely to be needed.

Answer: Speculative execution

Q2) The raw speed of the microprocessor will not achieve its potential unless it is fed a constant stream of work to do in the form of computer instructions.

A)True

B)False

Answer: True

Q3) At the most fundamental level,the speed of a processor is dictated by the pulse frequency produced by the clock,measured in cycles per second,or _________.

Answer: Hertz (Hz)

Q4) _________ metric are required for all reported results and have strict guidelines for compilation.

Answer: Base

Q5) ___________ is the ability to issue more than one instruction in every processor clock cycle.

Answer: Superscalar execution

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Chapter 3: A Top-Level View of Computer Function and

Interconnection

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Q1) Each data path consists of a pair of wires (referred to as a __________ )that transmits data one bit at a time.

A)lane

B)path

C)line

D)bus

Answer: A

Q2) A(n)________ interrupt is generated by an I / O controller to signal normal completion of an operation,request service from the processor,or to signal a variety of error conditions.

Answer: I / O

Q3) Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy.

A)True

B)False

Answer: True

Q4) The most common classes of interrupts are: program,timer,I / O and ________.

Answer: hardware failure

Page 5

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Chapter 4: Cache Memory

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Q1) To achieve greatest performance the memory must be able to keep up with the processor.

A)True

B)False

Q2) For random-access memory,__________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use.

A)memory cycle time

B)direct access

C)transfer rate

D)access time

Q3) The ________ rate is the rate at which data can be transferred into or out of a memory unit.

Q4) The L1 cache is slower than the L3 cache.

A)True

B)False

Q5) __________ memory is a facility that allows programs to address memory from a logical point of view,without regard to the amount of main memory physically available.

Q6) __________ memory consists of peripheral storage devices,such as disk and tape.

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Chapter 5: Internal Memory

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Q1) Flash memory is only used for internal memory applications.

A)True

B)False

Q2) RAM,ROM,PROM,EPROM,EEPROM,and flash memory are all examples of __________ memory types.

Q3) The two traditional forms of RAM used in computers are DRAM and SRAM.

A)True

B)False

Q4) The advantage of RAM is that the data or program is permanently in main memory and need never be loaded from a secondary storage device.

A)True

B)False

Q5) A __________ contains a permanent pattern of data that cannot be changed,is nonvolatile,and cannot have new data written into it.

A)RAM

B)SRAM

C)ROM

D)flash memory

Q6) __________ works by creating resistance rather than directly storing charge.

Page 7

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Chapter 6: External Memory

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Q1) RAID level ________ has the highest disk overhead of all RAID types.

A)0

B)1

C)3

D)5

Q2) The areas between pits are called _________.

A)lands

B)sectors

C)cylinders

D)strips

Q3) __________ is the standardized scheme for multiple-disk database design.

A)RAID

B)CAV

C)CLV

D)SSD

Q4) The time required to move the disk arm to the required track is the __________.

Q5) The transfer time to or from the disk does not depend on the rotation speed of the disk.

A)True

B)False

Page 8

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Chapter 7: Input Output

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Q1) A ________ is used to connect storage systems,routers,and other peripheral devices to an InfiniBand switch.

A)target channel adapter

B)InfiniBand switch

C)host channel adapter

D)subnet

Q2) The ________ command is used to activate a peripheral and tell it what to do.

A)control

B)test

C)read

D)write

Q3) An I / O module that takes on most of the detailed processing burden,presenting a high-level interface to the processor,is usually referred to as an _________.

A)I / O channel

B)I / O command

C)I / O controller

D)device controller

Q4) A ________ controls multiple high-speed devices and,at any one time,is dedicated to the transfer of data with one of those devices.

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Chapter 8: Operating System Support

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Sample Questions

Q1) The _________ scheduler determines which programs are admitted to the system for processing.

A)long-term

B)medium-term

C)short-term

D)I / O

Q2) The _________ defines the repertoire of machine language instructions that a computer can follow.

A)ABI

B)API

C)HLL

D)ISA

Q3) In an _________ system the user / programmer interacts directly with the computer,usually through a keyboard / display terminal to request the execution of a job or to perform a transaction.

Q4) Privileged instructions are certain instructions that are designated special and can be executed only by the monitor.

A)True

B)False

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Chapter 9: Number Systems

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Q1) In any number,the leftmost digit is referred to as the __________ digit because it carries the highest value.

Q2) A number with both an integer and fractional part has digits raised to both positive and negative powers of 10.

A)True

B)False

Q3) In the decimal system,________ different digits are used to represent numbers with a base of 10.

Q4) Which digit represents "hundreds" in the number 8732?

A)8

B)7

C)3

D)2

Q5) A nibble is a grouping of four decimal digits.

A)True

B)False

Q6) The rightmost digit is called the _________ digit.

Q7) (2 x 10-1)+ (5 x 10-2)+ (6 x 10-3)represents the number _________.

Q8) The decimal system has a radix of _________.

Q9) Binary digits grouped into sets of four bits are called a _________. Page 11

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Chapter 10: Computer Arithmetic

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Q1) With a fixed-point notation it is possible to represent a range of positive and negative integers centered on or near 0.

A)True

B)False

Q2) Actual floating-point representations include a special bit pattern to designate zero.

A)True

B)False

Q3) An advantage of biased representation is that nonnegative floating-point numbers can be treated as integers for comparison purposes.

A)True

B)False

Q4) Booth's algorithm performs more additions and subtractions than a straightforward algorithm.

A)True

B)False

Q5) The _________ is that part of the computer that actually performs arithmetic and logical operations on data.

Q6) The use of subnormal numbers is referred to as _________ underflow.

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Chapter 11: Digital Logic

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Q1) A combinational circuit can be defined by Boolean equations,truth table,and

Q2) Binary addition is exactly the same as Boolean algebra.

A)True

B)False

Q3) ________ are used in digital circuits to control signal and data routing.

A)Multiplexers

B)Program counters

C)Flip-flops

D)Gates

Q4) A _______ is an electronic circuit that produces an output signal that is a simple Boolean operation on its input signals.

A)gate

B)decoder

C)counter

D)flip-flop

Q5) Logical functions are implemented by the interconnection of decoders.

A)True

B)False

Q6) The simplest form of sequential circuit is the _________.

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Chapter 12: Characteristics and Functions

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Q1) The collection of different instructions that the processor can execute is referred to as the processor's _________.

Q2) Procedures do not allow programming tasks to be subdivided into smaller units.

A)True

B)False

Q3) The operation to be performed is specified by a binary code known as the operation code.

A)True

B)False

Q4) Source and result operands can be in one of four areas: main or virtual memory,immediate,I / O device,and _________.

Q5) ________ instructions are those that change the format or operate on the format of data.

Q6) The operation of the processor is determined by the instructions it executes,referred to as _________ or computer instructions.

Q7) A branch can be either forward or backward.

A)True B)False

Page 15

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Chapter 13: Addressing Modes and Formats

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Q1) The simplest form of addressing is __________ addressing.

Q2) For addresses that reference memory the range of addresses that can be referenced is not related to the number of address bits.

A)True

B)False

Q3) The method of calculating the EA is the same for both base-register addressing and indexing.

A)True

B)False

Q4) The _________ was designed to provide a powerful and flexible instruction set within the constraints of a 16-bit minicomputer.

A)PDP-1

B)PDP-8

C)PDP-11

D)PDP-10

Q5) The value of the mode field determines which addressing mode is to be used.

A)True

B)False

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Chapter 14: Processor Structure and Function

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Q1) Instruction pipelining is a powerful technique for enhancing performance but requires careful design to achieve optimum results with reasonable complexity.

A)True

B)False

Q2) The ________ determines the opcode and the operand specifiers.

A)decode instruction

B)fetch operands

C)calculate operands

D)execute instruction

Q3) It is possible to improve pipeline performance by automatically rearranging instructions within a program so that branch instructions occur later than actually desired.

A)True

B)False

Q4) The _________ stage includes ALU operations,cache access,and register update.

A)decode

B)execute

C)fetch

D)write back

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Chapter 15: Reduced Instruction Set Computers

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Q1) A large number of general-purpose registers,and / or the use of compiler technology to optimize register usage,a limited and simple instruction set,and an emphasis on optimizing the instruction pipeline are all key elements of _________ architectures.

Q2) The MIPS R4000 processor chip is partitioned into two sections,one containing the CPU and the other containing a _________ for memory management.

Q3) All MIPS R series processor instructions are encoded in a single ________ word format.

A)4-bit

B)8-bit

C)16-bit

D)32-bit

Q4) A tactic similar to the delayed branch is the _________,which can be used on LOAD instructions.

A)delayed load

B)delayed program

C)delayed slot

D)delayed register

Q5) The acronym CISC stands for _________.

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Chapter 16: Parallelism and Superscalar Processors

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Q1) The essence of the ________ approach is the ability to execute instructions independently and concurrently in different pipelines.

A)scalar

B)branch

C)superscalar

D)flow dependency

Q2) Superscalar instruction issue policies are grouped into the following categories: in-order issue with in-order completion,out-of-order issue with out-of-order completion,and ____________.

Q3) With ____________ any number of instructions may be in the execution stage at any one time,up to the maximum degree of machine parallelism across all functional units.

Q4) The _________ predicts the instruction stream,fetches instructions from the L1 instruction cache,and places the fetched instructions into a buffer for consumption by the decode pipeline.

Q5) ARM architecture has yet to implement superscalar techniques in the instruction pipeline.

A)True

B)False

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Chapter 17: Parallel Processing

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Q1) Uniprocessors fall into the _______ category of computer systems.

A)MIMD

B)SIMD

C)SISD

D)MISD

Q2) SMPs,clusters,and NUMA systems fit into the ________ category of computer systems.

A)SISD

B)MIMD

C)SIMD

D)MISD

Q3) ________ provides service to customers in the form of software,specifically application software,running on and accessible in the cloud.

A)PaaS

B)CaaS

C)SaaS

D)IaaS

Q4) Computer systems that fall into the ________ category have a set of processors that simultaneously execute different instruction sequences on different data sets.

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Chapter 18: Multicore Computers

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Sample Questions

Q1) The generic timer handles interrupt detection and interrupt prioritization.

A)True

B)False

Q2) The principal building block of the IBM zEnterprise EC12 mainframe is the __________ .

Q3) With _______,register banks are replicated so that multiple threads can share the use of pipeline resources.

A)SMT

B)pipelining

C)scalar

D)superscalar

Q4) The increasingly difficult engineering challenge related to processor logic is one of the reasons that an increasing fraction of the processor chip is devote to the simpler memory logic.

A)True

B)False

Q5) The big.Little architecture uses a combination of ARM Cortex-A7 and Cortex A-15 cores.

A)True

B)False

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Chapter 19: General-Purpose Graphic Processing Units

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Q1) The _________ scheduler breaks up each thread block it is processing into warps.

Q2) The fundamental building block of the Gen8 architecture is the ________ unit.

Q3) __________ are caused by limited SFUs,double-precision multiplication,and branching.

A)Structural hazards

B)RAW data hazards

C)Vertical hazards

D)Latency hazards

Q4) A SoC product architect can create product families or a specific product within a family by placing a single slice or multiple slices on a SoC chip.

Q5) A __________ program can be divided into three general sections: code to be run on the device,code to be run on the host,and the code related to the transfer of data between the host and the device.

Q6) The grid and the block need to have the same dimensions.

A)True

B)False

Q7) CUDA C is a C / C++ based language.

A)True

B)False

Page 22

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Chapter 20: Control Unit Operation

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Q1) The _______ designates the state of the processor in terms of which portion of the cycle it is in.

A)ICC

B)BSA

C)ALE

D)ISC

Q2) The ________ is connected to the data lines of the system bus.

A)MAR

B)PC

C)MBR

D)IR

Q3) Which of the following is an Intel 8085 external signal?

A)CLK(OUT)

B)read control

C)HOLDA

D)all of the above

Q4) Each phase of the instruction cycle can be decomposed into a sequence of elementary micro-operations.

A)True

B)False

Page 23

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Chapter 21: Microprogrammed Control

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Q1) The control unit design is very flexible.

A)True

B)False

Q2) Which of the following is a LSI-11 microinstruction?

A)add word

B)test word

C)Jump

D)all of the above

Q3) The _________ is a 32-bit ALU with 64 registers that can be configured to operate as four 8-bit ALUs,two 16-bit ALUs,or a single 32-bit ALU.

A)PDP-11

B)8832

C)3033

D)8818

Q4) The principal disadvantage of a microprogrammed unit is that it will be somewhat slower than a hardwired unit of comparable technology.

A)True

B)False

Q5) A sequence of instructions is known as a ___________,or firmware.

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