Complex Systems Design Management Proceedings of the Fourth International Conference on Complex Systems Design Management CSD M 2013 1st Edition John Fitzgerald
Complex Systems Design Management Proceedings of the Fifth International Conference on Complex Systems Design Management CSD M 2014 1st Edition Frédéric Boulanger
This book is about how to design the most complex types of digital circuit boards used inside servers, routers, and other equipment, from high-level system architecture down to the low-level signal integrity concepts. It explains common structures and subsystems that can be expanded into new designs in different markets.
The book is targeted to all levels of hardware engineers. There are shorter, lower-level introductions to every topic, while the book also takes the reader all the way to the most complex and most advanced topics of digital circuit design, layout design, analysis, and hardware architecture.
Istvan Nagy received a Master’s degree in electrical engineering (MSC) from the Budapest University of Technology and Economics, Faculty of Electrical Engineering and Informatics, in Budapest, Hungary, in 2006. He has worked in several countries and industries, including on highend data center networking equipment design in Silicon Valley as well as aerospace and industrial computing board design in Europe and Florida.
Complex Digital Hardware Design
Istvan Nagy
Designed cover image: Meta Big Basin base board routing in the PCB layout from The Open Compute Project, the screenshot from the layout design is used for illustration under the Open Compute Project Hardware License (Permissive) Version 1.0 (The Open Compute ProjectHL-P) signed by Facebook, Inc. (Meta Platforms, Inc.).
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15.1
About the Author
I have been working as a hardware design engineer for 18 years, after a 13-year student hobby electronics design “career”. I worked in several different countries and industries, including industrial computers, military/aerospace boards, telecom, and leading-edge data center network equipment design in Silicon Valley. This allowed me not only to write about one specific type of product, but also to provide a wide-angle view that is applicable to many different designs the readers might be working on. Now I am sharing with you what I have learned and some of my own findings and ideas, too. Many of my designs were large multi-ASIC boards like line cards or appliance base boards. They utilized all the main large devices on the market, typically combinations of different types of processing chips. For example, having a processor, several FPGAs, and network ASICs on the same board were common.
Over the years I have received a lot of advice from Istvan Novak, as well as the community of the Si-List, about understanding the more ambiguous SI problems. The companies I worked at and the world-class hardware teams they had provided me with opportunities to work on increasingly complex and leading-edge design projects with uncommon technologies and high-performance devices.
1 Introduction
The purpose of this book is to show all aspects of a hardware design engineer’s job in the more high-end digital board segments. This individual is sometimes called a hardware engineer, hardware design engineer, electrical engineer, electronics design engineer, CCA, or PCA engineer. The book is focused mainly on low-level detailed circuit implementation, but it also discusses highlevel aspects like systems and manufacturing. This book is about advanced hardware design, so it is assumed that the reader has an EE degree and has already designed some lower-complexity digital circuit boards. There are short introductions to all topics, but the focus is on more advanced material.
This book includes a large amount of signal integrity topics, about half of the book’s volume, and it focuses on how to apply them in a corporate design project by the designer. The rest of the topics are about hardware architecture and various engineering activities that are loosely affected by signal integrity in various ways. Complex hardware is always high speed, and it includes a large number of high-speed signals at high density. High-density, high-speed design is different from basic high-speed design with few high-speed signals. The large number of them at close proximity creates the need for advanced SI/PI mitigation solutions, which we study in this book. For example, a digital chip that has 400 instead of 4 signals running at 56Gig dissipates 400Watts, requires very high-end VRM and power plane designs, and requires a fanout pattern that takes up a very small board area for each controlled impedance via structure. Complexity also has emergent properties. Complex hardware has structures and functional circuits that do not exist in simple circuit boards. Complex boards are not simply more of the same that we see in simpler boards. For example, a microcontroller board would not need a second processor for system management. A laptop motherboard would not need several FPGAs.
The approach here is to present the intersection of signal integrity, layout constraints, firmware, and functional hardware architecture—specifically, how decisions in one domain affect the decisions that have to be made in the other domains. There is someone in the project team who has to understand all those things as one in full context, and this individual is the hardware design engineer, the target audience. This work is a bit like management, especially at large companies, and it requires making arrangements with multiple other departments daily, while also doing detailed hands-on work. Several good books on signal integrity are available, but they were written for fulltime signal integrity engineers by full-time signal integrity engineers, and they focus on analysis. A hardware design engineer has several other responsibilities too, while still required to deliver SI excellence. A few books are available on hardware architecture, but they are written mainly from the marketing and user point of view and are not about how to design the underlying detailed circuits for them or why they chose those elements for the block diagram. This book seeks to improve understanding of both areas by talking about the combination of SI-driven detailed design and multi-level hardware architecture design.
Complex hardware is basically a circuit board with over 1,000 components on it and with chips that have over 600 pins, usually multiple large devices with thousands of pins each. The largest boards might have 10,000 to 20,000 components, including multiple large ASIC chips and FPGAs. Having 4k…8k are actually very common in data center network hardware and other equipment that regular consumers will never see in real life, while they all use them unknowingly every day when streaming videos or accessing media websites or smartphone apps. Hardware engineering is unlike other sciences—hardware engineers have to build new products out of several existing products. These existing products are silicon devices, other components made by third-party vendors and using board manufacturing technologies developed and marketed by service suppliers. Most of
this high-end data center equipment is designed in Silicon Valley (California), China, and Taiwan as well as in a few locales in Texas, Oregon, and Massachusetts. Still complex and high-speed but not the leading edge (mil/aero, telecom and consumer, with 1000…2000 components) equipment is designed at several other places, while these jobs are far from being available in every city, state, or country.
No one starts their career with a large multi-ASIC board design. That comes a few years later. Every designer has to start small, with a two-layer board with a few small chips or transistors on it, hopefully during the student years or as junior engineers. Students might have to pay for their own PCBs and components, but it is worth it. We can order them online. They then take a slightly more challenging project next with a small microcontroller or CPLD, and then again slightly more complex, maybe an ARM CPU with some memory and other chips. Students should take the initiative and decide what they want to design, do it in their free time, and pay for it with their own money. Do not wait for the professor to tell you to design it. While working as junior engineers, we have to lobby our managers to give us some cool design projects. This book does not explain these very first designs; rather, it picks up at that stage when the reader has already done a few smaller to medium-sized projects. This is because complex hardware design is a separate discipline from basic electronics, and it builds on top of it.
In the hardware industry detailed design files and drawings are considered secrets, so the only design examples used in the book are from made-up partial designs, from open-source projects, and from some of my old hobby projects. As a learning exercise, we can analyze how some of the open-source systems are built and designed and what parts and parameters go into it by reading the specifications or by reviewing their schematic and PCB layout files. This book mainly shows block diagrams and a few specific details, but the reader can find the actual schematic and layout files for reviewing the complete designs on the Internet. Any commercial design owned by different companies details cannot be shared here. Instead, specific design feature concepts are discussed, one detail at a time, or publicly available design files or on made-up partial designs. Several made-up singleissue examples are also used to demonstrate the effect of a certain parameter. Component information is provided only as long as it is also available in public datasheets, although newer under-NDA components are very similar to them, they would be designed into boards almost the same way. For most of the images and demonstrations free software tools were used, simply for the convenience of book publishing, although in the text there is discussion based on commercial software also. In real engineering we utilize various expensive commercial software, and our design files never get published as open source.
This book will refer to several standards, but explanations will be given only as much as necessary to understand hardware features or design activities. We will not be just listing the contents of each standard document for the sake of being precise or academic. Most standards have to be purchased to obtain the actual numbers, so they are omitted here. A big portion of most standards focus on how the chip designers have to implement a feature, and that is outside of the scope of this book.
In this book we use the “slang” ASIC for any large high-bandwidth digital chip, including CPUs, GPUs, FPGAs, and actual ASICs, to simplify the text. Designing boards for these four types is very similar, and most chapters are applicable to all of them. Another convention in the book is the many references to “speed” in Gbps, that is for each signal net, it does not refer to the total bandwidth of a multi-lane port, as the difficulty level for our work depends on the speed of each signal.
Most of the concepts and solutions described in this book are very common in the high-tech hardware industry—at least dozens of companies and hundreds of engineers practice them every day. Thus, they can be considered industry-wide best practices or de facto standards. Some of the ideas in the book are unique; however, they have been developed to make our work easier or more effective. For example, special diagrams made for helping the designer with pin mapping or with error checking. The data center networking industry has taken the lead in hardware technology and
high-speed design in recent decades, and brand-new solutions and inventions have become common practice, having trickled down to the computing hardware industry a few years later (like the use of 56Gig SERDES), then, a few more years later, trickling down into other industries with a much larger number of companies, for example consumer and industrial electronics, medical devices, and aerospace. Thousands of engineers around the world are now starting to implement in their designs some of the things that we did 10 years ago in Silicon Valley. The design complexity in these downstream industries is not growing that much, but the processing performance and the high-speed interface implementations are.
The language and explanations here are more similar to two engineers talking at the water cooler or at a whiteboard rather than a university lecture. But we still have to involve some scientific topics like S-parameter analysis, and there are plenty of equations and flow charts also.
This book does not just provide data from expert to expert. This is also not a user manual or a datasheet or project spec. It is not just basic “information”. Hardware engineering requires a kind of thinking different from most other engineering fields. We obsess for days over details that someone might dismiss as obvious. For example, “provide correct data to the simulator” . . . okay, but how do I know it is correct? Most of the time in hardware engineering we have to make decisions based on severely limited information, and this is different from simply deducting one parameter from two other parameters. A lot of design work requires reverse thinking, trying to guess what we need to do put in the design to arrive to a certain outcome or what error can cause a certain outcome. We also have to see everything through statistical (not actual) behavior and through risk management concerns. We often reiterate things everyone in the team knows for clarity, because we need super level clarity and precision for hardware engineering. Even common circuits behave differently in different boards. Expert designers know it when they see it, others stare at it without seeing it. We also use common tools in uncommon ways, and we use many lesser known tools. Many explanations in this book seem preachy or lengthy; it employs low-level philosophy to help bridge that gap. In hardware teams we get bogged down arguing these things all the time before a design or test action can be properly taken or interpreted. So it is a big part of our work—perhaps not in simple hardware projects but in complex projects for sure.
A lot of design effort goes into risk management. That is reducing the risk of getting completely nonfunctional and unfixable prototypes, and the risk of shipping unreliable production boards. This is done through various analysis tasks (spreadsheets, diagrams, and simulation) and by design fortification (like putting zero ohm resistors in the schematic and using proper power sequencing) that might seem excessive to inexperienced people. The causes of dysfunctional or unreliable hardware are often very convoluted, one will fully understand them only through experience. This is why most of these techniques are (high-tech) industry-wide best practices, followed by competent people, so most engineers do not have to create bad designs to learn from them. On the other hand, these are not basic fully documented practices such as those found in older professions (chemistry, machinery), so we cannot assume that all engineers and all companies just know it all. This book is intended to help readers learn about them so they can become more common outside of the data center industry.
Other sources of knowledge we can follow are the conferences relevant to hardware solutions. The most important conference is the DesignCon, followed by others like EdiCon, OCP Summit, and the Hot Chips Conference.
BOOK ORGANIZATION
The learning content of this book is organized in seventeen chapters.
Chapter 2 is titled “Digital Circuits”. First we discuss digital signaling standards, then move onto slightly more complex standards involving signal terminations and continue in discussing basic bit-level and bus-addressing I/O protocol standards. This chapter also discusses a few key interface blocks used by many larger chips, like JTAG ports, parallel bus interfaces, and SERDES IPs.
Finally additional I/O features are discussed like debouncing, ESD protection, data corruption, and security.
Chapter 3 is titled “Major Interfaces”. It continues the line of complexity where the previous chapter left off by discussing complex protocol standards like Ethernet, PCI-Express, and other modern SERDES-based high-performance interfaces.
Chapter 4 is titled “Power Supply Circuits”. It describes power supply or voltage regulator module (VRM) designs from the point of view of the digital hardware designer. We digital designers mostly focus on digital circuits, but one type of analog circuit—the power supply circuit—is always present in our designs. Some aspects of these VRMs require the digital designer to handle, like power sequencing, and any features that affect or are dependent on our load ASIC chips. It is important to understand how we digital engineers work together with analog power supply engineers to ensure that the analog control loops of each VRM are fine tuned to work on our digital board.
Chapter 5 is simply titled “Components”. This chapter starts out with explaining the design aspects of adding small parts into our complex circuits by describing not really the small components themselves but rather how they fit into our complex designs. After this, other slightly more complex components, the programmable active parts are introduced in several categories, like peripheral controllers, retimers, analog to digital converters, clocking chips, and bridge chips. Different connector types and mechanical parts are also discussed. This chapter ends with a discussion of the different memory chips and modules that we use.
Chapter 6 is titled “Main Chips”. It is a continuation of the previous chapter, but focuses on the three main categories of the main large chips, the processors, FPGAs (Field Programmable Gate Arrays), and the ASICs (application Specific Integrated Circuits). Each has several subcategories that are introduced, together with category-specific design considerations.
Chapter 7 is titled “Hardware Architecture”. It is all about how we put all these elements we learned about in all the previous chapters into complex design concepts, mainly at the block diagram level. This chapter also discusses how the different system signals of the large and small chips are connected together to create different subsystems. These are the data plane, control plane, management plane, glue logic, and power and clocking subsystems. Once we are able to create system architectures, we often divide them into multi-board systems, as described later on in this chapter. Finally, three complex board architecture examples are presented.
Chapter 8 is titled “System and Chassis”. It describes the created hardware architectures from a more practical outside view or mechanical view, as they form a complete product or a system. This chapter also introduces typical systems from different industry segments and their design and internal architectural considerations, with several examples from industry, science, and aerospace, to the different types of high-end data center hardware products. These include servers, switches, and appliances.
Chapter 9 is titled “Hardware-Firmware Integration”. It discusses how firmware teams develop their firmware and software that run on our hardware systems, and how we hardware engineers have to participate in teamwork with them. This includes data we have to prepare for them, and what we can expect from them. Some of the firmware is created for the sole purpose of testing out our new prototype hardware designs.
Chapter 10 is titled “Timing Analysis”. It describes the complex topic of timing analysis that we sometimes have to perform on the non-SERDES types of parallel or serial interfaces. The purpose of this work is to generate trace length constraints for the layout design as well as to verify the reliability of the design.
Chapter 11 is titled “Signal Integrity”. It discusses signal integrity from the point of view of the designer, not the full-time analyst. The hardware designer has to understand SI concepts, when or where to apply them, and how to interpret the results of any analysis. This chapter starts with considering scattering-parameters from stolen from RF analog engineering, then describes SI concepts that can ruin our designs, and explains what simulations really do and how to use them. It closes with the different fields of SERDES link analysis.
Chapter 12 is titled “PCB Materials and Stackups”. It is related to signal integrity but focuses on how the PCB materials affect it. This chapter also explains trace impedance control, insertion loss control, various material effects, and how to design our own PCB layer stackup.
Chapter 13 is titled Power Integrity. It talks about power integrity that deals with the highfrequency behavior of the voltage rails that feed our ASIC chips. We learn about the elements and several design and analysis methods. An important part of the design is the decoupling capacitor selection, which is described through several different methods.
Chapter 14 is titled “Initial Design”. This refers to all the engineering work that is being done in a project up to the point just before starting the PCB layout design. The various documents we have to produce, the analysis we have to perform, the way we select components and blocks for our block diagrams, and a little bit about how schematics of complex hardware differ from schematics of simple board designs are all explained here. Analysis is not just SI/PI or circuit simulation. We carry out a lot of analysis with a calculator and with spreadsheets and drawings or diagrams like floorplans before we are ready to settle down with the final hardware architecture and detailed schematics.
Chapter 15 is a long and important chapter titled “PCB Layout Design”. This was not meant for layout only engineers and not as a layout tool training. It is more about how the hardware design engineer has to oversee and instruct the layout engineer’s work on a daily basis; about what highspeed structures we want to see in the PCB. We have to understand the layout design and fabrication elements as well as the high frequency behavior of all of them. The design tool features that were developed to make the first computers and the more modern equipment accelerate and sometimes limit our ability to tame the high-frequency behavior. Complex high-speed hardware designs heavily rely on the high-speed or high-frequency behavior of the PCB layout and our methodologies employed to control them through constraints and layout instructions/reviews. We will read about how to design the different hardware portions, like decoupling networks, VRM subcircuits, SERDES link traces and vias, power planes, and memory interfaces.
Chapter 16 is titled “Prototyping”. Once we have completed the hardware and layout design, our board gets manufactured, and we have to spend time in what is called the bring-up process. This is a combination of testing and measuring as well as debugging and inventing weird solutions to counteract our own design mistakes. Several interesting tools have been developed to help us with this process, for example live system boundary scan, command line Linux tools, and VRM test equipment.
Chapter 17 is titled “Measurements”. It describes the measurements that we take in prototyping, during design verification testing (DVT), or sometimes in production debugging. In this book we focus on the measurement types that are more relevant to our complex high-speed hardware. These are limited oscilloscope measurements on live signals, passive PCB signal trace VNA (Vector Network analyzer) measurements, and power delivery system impedance measurements with a power-VNA and on-chip eye capture.
Chapter 18 is titled “Manufacturing”. It discusses the larger scale manufacturing of our debugged and fixed designs. This is often also applicable to making the prototypes. We still have to do debugging and testing in manufacturing, which is described in this chapter. Other activities related to manufacturing, such as dealing with returned boards and analyzing them for design improvement as well as statistical reliability analysis and design considerations, are reviewed.
2 Digital Circuits
We studied basic digital circuits at university, but, in practical hardware design, there are more considerations required for designing these. These can be supporting circuits to the main chips or they can be part of the glue logic, the management subsystem, or even participate in high-bandwidth interfaces as minor functions like level translation. We also need to understand in detail the portions of the main chips that interact with other chips. Designing in any digital chip is done through interfacing their digital circuits to other chips.
2.1 I/O STANDARDS
An I/O standard is a set of standard parameters that are defined in a standard specification document that allows different chip and board vendors to build devices that can communicate with thirdparty devices reliably. The main difference between different I/O standards at the physical level is their voltage thresholds for logic low and logic high data value, and the termination schemes used. These I/O standards are innovations created for the purpose of achieving higher speed transmission than the previous I/O standards had, with little added cost.
We use two types of digital signals, the traditional “single-ended” signals and the “differential pairs”. Memory interfaces have been pushing single-ended signaling above 5GHz, while all other types of interfaces switched over to differential above 150MHz. Single-ended is simply one single net carrying a voltage relative to the ground plane, with input logic voltage level thresholds also defined relative to the ground. Examples of I/O standards in the single-ended type are the most common CMOS with various different voltage options, the older TTL, and some newer SSTL types. Differential pairs (diffpairs in short) are made up of a single-ended signal with another singleended signal that has the opposite value at all times, one versus zero or vice versa. Once the diffpair signals arrive to the chip input pins from the PCB trace, they are not compared against the ground level; rather, they are compared to each other. Usually, we use net names like XXX_P for the positive “leg” of the pair, and XXX_N for the negative leg. If the voltage on _P is larger than the voltage on _N then it is a logic high (one) level, otherwise a low (zero) level. The actual voltage on them relative to the ground is not too important, but it is normally either slightly below or above a “DC bias” voltage. On the PCB layout the two legs are routed together at once, with constant spacing between them maintained by the design tool, and with length matching enforced by constraints (explained later).
Most standards have an upper limit on toggling speed, or a speed versus bus length combination limit due to their terminations not being impedance matched to the trace impedance, and their timing architecture running out of time. Single-ended standards simply have absolute voltage level requirements, differential standards have differential, and common mode (bias) voltage level requirements. Some interfaces are AC-coupled, with a capacitor in series. They work only if the low frequency content is eliminated from the data stream by applying some type of encoding, and the line never stops toggling for more than a few bit periods. If AC-coupling is used then the bias (matching between transmitter and receiver) requirement is eliminated. Typically, 100 to 220nF ceramic capacitors are sufficient. The outputs have thresholds (guarantees), and the inputs also have thresholds (requirements), arranged in a way that the worst level output signal with worst-case PCB signal degradation will still meet the minimum input level requirements with a margin. This can be seen in Figure 2.1.
Differential signaling was invented to improve signal recovery from noisy and lossy channels. Common mode interference is less harmful to received differential signals, and we can
recover data even after the single-ended amplitude has degraded 5–10 times. Differential signals are often displayed on an eye diagram, where the inside is the vertical eye opening (minimum requirement) and the outside is the amplitude (must be less than this to avoid stressing the circuits and improve signal to noise ratio). A single-ended signal would have an input eye height requirement as much as H >V IHMIN -V ILMAX , basically about 0.3*VDD, while differential signals have a much smaller requirement, basically as much as the input differential amplifier minimum input voltage H >Noise+Vout/Gain, about 0.05*VDD. Single-ended inputs that use a centered reference voltage threshold instead of fixed logic H/L thresholds, like the SSTLII standard, also have a small input eye height requirement, similar to differential inputs. The voltage thresholds are different in every I/O standard, as we can see in Table 2.1. The voltage level difference between the input and the output thresholds is the allowance for noises. These noises include crosstalk, reflection, insertion loss, and EMI interference. Usually we have 0.1 to 0.3*VDD, or at least 100mV gap available. Some devices (seen on their datasheets) violate the standard thresholds, so when using them we need to do a compatibility analysis (spreadsheet), checking whether we have at least 100mV gap at the low level, and a few hundred at the high level, between the transmitting and the receiving chip.
Voltage bias is part of many differential I/O standards. This pulls the signal line towards a certain voltage, which might be the same as VDD, GND, VDD/2, or any arbitrarily generated voltage level (VTT). AC-coupling is used when the transmitter and receiver chips have different and un-documented bias voltage levels. If the transmitter and receiver have (or might have) different bias voltage, then we have to use AC-coupling to prevent the two bias circuits from fighting each other (back-drive) while distorting and clipping the signal. If one chip’s datasheet does not mention the bias voltage level, then we have to assume it is a different level than our other chip has, and we have to AC couple them. If the two devices are powered up at different times, for example if they are on different boards, then AC-coupling can prevent the biasing circuit from being damaged by the unpowered device shorting the signal lines to ground. We also have to check the chip’s datasheet or reference design schematic for any clues about unusual cases of AC-coupling.
FIGURE 2.1 Signal logic levels in general.
2.1.1 TerminaTions and reflecTions
Single-ended I/O standards are usually used at a slow enough data rate so that they do not need termination resistors, except if the traces are very long or the bus is really fast. Even signals that are much slower than 100MHz will still suffer from reflections since the long traces create a slow time constant for the reflection arrival (ringing) that can very well be within the ballpark of the bit time. This is when the traces become transmission lines. Low toggle rate (low-speed) signals might also have very fast rise times if the chip uses similar buffers on its high-speed and low-speed signal outputs. The reflections are naturally mitigated if the signal rise time is so slow that it does not finish rising by the time the reflected waves arrive. This creates a basic rule that terminations and trace impedance control are required if rise_time < 2* FT, where FT is the flight time of any signal through a specific length of PCB trace or cable, calculated as FT = TraceLength* SQRT(DK) / 11.8, in nanosecond and inch. The “propagation delay” is the rise time plus the flight time. For example, a 10MHz bus has 100ns bit time, but on a 5ft cable arrangement we can have reflections arriving at 2N*10ns, that is 20, 40, 60ns timestamps. We cannot use much more than 60ns rise time as it would eliminate the whole bit time. These cases require trace impedance control and some kind of termination at input pins of active devices, even on 3.3V CMOS and 5V TTL signals that are usually not terminated. They are designed to operate with low currents that would create unrecognizable logic levels when using trace impedance matched regular terminations. Terminations pull a lot of current, depending on I/O voltage. This is why these types of interfaces use AC termination, series termination, or sometimes very low I/O voltage to get within the range of the I/O buffer current drive capability. The designer has to calculate or better simulate the DC current that the termination would pull to see whether it is within the capability of the chip’s output buffer.
Terminations and trace impedance starts to matter above 10MHz usually, in the same time trace impedance cannot be maintained to be flat and frequency independent below about 10MHz. It is fortunate that at the frequencies we need it, we are able to use impedance matched terminations and traces. Below 10MHz there is still a trace impedance, but it varies much with frequency, so only sine waves could have matched impedance, not wide band digital signals.
Some signals that toggle slowly in the few MHz or few mHz range are usually considered “slow signals” that do not require termination and impedance control, except if they are driven by chips that also drive very fast (like DDR3) signals on the same pin type. In that case they will have fast rise times and trigger the equation above. So below 10MHz we have to check what kind of buffer drives them. If they do need termination then we have to calculate the impedance for them at the frequency of their rise time (f=0.35/t_r), or at the 5th harmonic of their half baud rate, not at their data rate. For clock signals it is either the knee frequency or the 5th harmonic of their clock frequency. SERDES signals are analyzed at the half baud rate, called the Nyquist frequency. Signals driven by power/system management glue logic, microcontrollers, open drain buses, logic gates, and EEPROMs have slow enough rise times to use them without impedance control and matched termination. Instead of calculating the equation for every signal to determine the termination need below 10 to 200MHz data rate, we use categories and interface or device types. Another clue is if the buffer is incapable of driving enough current into a matched termination, then it also does not need impedance-controlled traces. Above 1.5V VIO the currents are unattainable for most chips. At 1.8V it would be 24mA, at 3.3V it would be 217mA.
Differential I/O standards always use terminations, especially differential clocks. Some chips have built-in input termination resistors (on-die termination, ODT), others do not; unfortunately, in many cases it is not clearly documented in the datasheet. What we can do is to add some DNP termination resistors at the receiver input. This is especially a problem for reference clock inputs. The high-speed data lines above 2Gbps always have impedance matched integrated terminations, so adding extra DNP resistors on board would distort the signal through stubs and parasitic capacitance. Sometimes a resistor in the schematic is a bias resistor to create current on the output driver and drop voltage on it, not a termination resistor. But if its value matches the line impedance, then it also
acts as termination, as is common with CML and its 50 Ohm pull up. HCSL and LVPECL outputs require biasing resistor pull-downs, at 49.9 Ohm and 130 to 200 Ohm, depending on the buffer’s supply voltage. The resistor might be integrated in the device—in that case we do not need it on the board. The datasheets should help in selecting the resistor value. Sometimes an input termination is between the signal and a VTT voltage generated by the receiver chip, or they require an asymmetrical Thevenin termination that biases the input to the required VTT level, while receiving an AC-coupled signal.
Termination location can be series at source/TX, or parallel at source, or parallel at far end (at load/RX, or at the end of a multi-drop bus line). Parallel termination resistor can connect a signal line to ground, to VDD, to VTT (termination voltage, usually VDD/2), or to the complement signal in a differential pair (differential termination). If we terminate to VTT then a voltage regulator is needed to produce the VTT voltage rail, usually a fast-acting source/sink-capable LDO or a small switching buck regulator. We also create a small power shape for the VTT voltage, called the “termination island”, usually on a surface layer so the many termination resistors can connect directly to it. We also need to provide decoupling to the termination island, around one 0402 100nF capacitor per 3 to 5 signals.
Parallel termination can also be a “Thevenin” type, when a 2*Z0 value resistor is connected from the signal to ground, and another one to VDD. This helps pulling the signal towards the middle. It will be more symmetrical, so it will spend equal time below the low threshold and above the high threshold, in case of symmetrical standards like LVCMOS1V8. The Thevenin termination also helps with reducing the output drive current capability requirement. For example, if we have a 1.5V CMOS system and want to do impedance matched end-termination with a 50 Ohm resistor to GND, then the output buffer will have to drive 28mA at high level and 0mA at low level. High-speed buffers with 28mA drive capability are almost non-existent. But if we use Thevenin termination of 100 Ohm up to the 1.5V rail and 100 Ohm to GND, with the same 50 Ohm impedance, now our buffer has to be able to drive only half as much, 14mA. More precisely +14mA when logic high, and -14mA when logic low. We can find many FPGAs that can do that, up to 16mA, or a few even to 24mA. The resistor value can be matched to Z0, or larger or smaller or asymmetrical to help with a signal that is already asymmetrical vertically. The upper resistor needs a return current path provided to the ground planes, so a decoupling capacitor needs to be placed at the Thevenin termination resistors, between VDD and GND. Alternatively to the Thevenin scheme we could use a single resistor terminated to VTT that is driven by a VRM at VDD/2 voltage. During a steady state this will consume less power than a Thevenin does with two resistors, as the Thevenin upper and lower resistors constantly draw current from the VDD power supply. All mentioned options of termination placement topologies can be seen in Figure 2.2 Figure 2.3 shows the waveforms produced by different termination schemes.
Termination resistor options on digital signals:
a) No terminations at all
b) Trace impedance (Z0) matched termination at both source (series) and far end (parallel)
c) Source series termination only, with impedance match
FIGURE 2.2 Termination options.
FIGURE 2.3
Mid-bus waveforms with different terminations, on a 12MHz 1V CMOS signal with an 18” long bus, LTspice simulations.
d) Source series termination only, but with Rs<<Z0
e) Source parallel termination only, with impedance match
f) Parallel at far end only, with impedance match
g) Parallel termination at source and load, with impedance match
h) Parallel AC termination at far end only, it is impedance-matched
i) Unmatched parallel termination at far end only, with Rp ~ 0.7 to 4*Z0
j) Parallel AC termination at source
Method a, the most basic option, is “No terminations at all”. We can omit having any terminations only if the round-trip flight time is (much) less than the rise time, and it is much less than the bit time (just waiting out the ringing, but silicon chips might still be stressed (MTBF reduction) by overshoot and undershoot). 2*FT < t RISE < t BIT
Method b is Trace impedance (Z0) matched termination at both source (series) and far end (parallel). Let us call it “full termination”. This eliminates all ringing and reflections from mismatch, but there might be small reflections from discontinuities. Inputs can switch at the incident wave without having to wait for the reflections to complete the final voltage level. The logic high singleended level will be half the VDD, formed by the voltage divider of the series TX and parallel RX termination resistors. It is only usable in differential I/O standards where the amplitude can degrade but the signal is still recovered by a difference amplifier. Half VDD signal level on CMOS is not detectable as a logic high level.
Method c is Source series termination only, with impedance match. With this scheme there will be one reflection from the far end, but that will be the last one. A device at the far end will see a little ringing, but mid-bus devices will see a two-step waveform, for them the signal setup time will be longer, as much as the roundtrip flight time instead of the length-based one-way flight time. If the capacitive load is high, it slows down the signals so much that they cannot reach proper logic levels at a given data rate. The RC delay has to be less than the round-trip delay, and the round-trip delay has to be less than half a bit time—ideally a lot less to meet setup timing too. It needs to be simulated. R*C << 2*FT << 0.5* t BIT
Method d is Source series termination only, but with Rs<<Z0, typically 5 to 33 Ohm. This is called a damping resistor. With this scheme there will be reflections from both ends, multiple times, called ringing, with overshoot and undershoot. A device at the far end will see a little ringing, but mid-bus devices will see a two-step waveform, a big step and a small step. The RC (damping resistor with bus capacitance) delay has to be comparable to the round-trip flight time but less than half a bit time—ideally a lot less to meet setup timing too. 2*FT < R*C << 0.5*t BIT . Overshoot peak voltage at the far end can be as high as Vpk=2*VDD*(Z0/(Z0+Zsrc)), while at the mid-bus point it is somewhat lower but it has a plateau there. The height of the plateau is VPL=VDD*(Z0/(Z0+Zsrc)) on rising edge and VPL=VDD-VDD*(Z0/(Z0+Zsrc)) on falling edge. Needs to be simulated. Any
source series termination slows down the rise time and limits the data rate. Sometimes we use it without trace impedance control, “hoping” that the trace impedance will be within 30 and 80 Ohms.
Method e is Source parallel termination only, with impedance match. With this scheme there will be one reflection from the far end, but that will be the last one, and the voltage levels are not reduced through voltage divider effect. A new transition should not start until the reflection returns to the source; this limits the speed. It requires strong output drive and low voltage signaling. Any mid-bus devices will see a two-step waveform, for them the signal setup time will be longer, as much as the round-trip delay. It is not useful for multi-drop buses, only for point-to-point topology.
Method f is Parallel termination at the far end only, with impedance match. It prevents reflections from the far end, so all devices on a multi-drop bus can act on the incident wave; there will not be a reflected wave, perfect waveforms. It requires the output drivers to have very high current capability, up to 60mA+ on 3.3V CMOS, that is not available with most chips, but 1 to 1.8V CMOS requires only up to 17 to 24mA in Thevenin mode that is available on some devices. It is mostly used on differential types with much smaller voltage levels. A 0.8Vpp differential driver would have to provide only 8mA into a 100 Ohm differential termination resistor.
Method g is Parallel termination at both the source and the load, with impedance match. This eliminates all ringing and reflections from mismatch and from discontinuities. This eliminates the voltage divider effect (distorted voltage levels) and allows high current drive and fast edge rates into capacitive load at a higher rate, and it consumes a lot of power. This is common at many gigabits per second rates. Typical SERDERS transceivers use calibrated on-die single-ended 50 Ohm (or Z0 matched) parallel terminations to internal BIAS voltage inside the far end RX circuit, and 50 Ohm pullup/bias resistors (current-mode driver that acts as termination too) to VDD inside the source TX circuit. This eliminates all reflections caused by termination values, but at high data rates there will be reflections from PCB discontinuities. Because of the bias VTT termination scheme, the signals must be AC-coupled. The internal termination resistor is automatically calibrated at power on to a 1% resistor that is connected to the ASIC calibration pin.
Method h is Parallel AC-termination at the far end only. It is an impedance-matched (39 to 60 Ohm) resistor with a capacitor (10pF to 10nF) in series. It reduces power consumption while still tries to match impedance, eliminating the multi-drop bus signal plateau. This only activates during the transitions and overshoots, and it should not affect the final logic levels. For this to work we need the capacitor to charge in less than half a bit time, but retain charge for the first period of ringing, which is dependent on trace flight time. These two requirements start to contradict above certain data rate or bus length. It needs to be simulated, but we can also use a formula: 2*FT < R*C << t BIT Often they calculate the capacitor value C=2*FT/R in ns and nF, with R=Z0, and max data rate is: f MAX=1/(10*2* FT)
Method i is Unmatched parallel termination at the far end only, with Rp ~ 0.7…4*Z0. This reduces overshoot amplitude, and overall ringing fade away time, while consuming less current from the output driver. We cannot consume more than the maximum output current listed in the datasheet. It is usable on LVCMOS; the output current is within grasp of a programmable FPGA I/O pin driver. The overshoot amplitude is very high, unless we combine it with a small value 5…15 Ohm source series termination.
Method j is Parallel AC termination at the source only, it is an impedance-matched (39 to 60 Ohm) resistor with a capacitor (10pF to 10nF) in series. It eliminates the second reflection at the source. It can be used in combination with far end termination types, instead of using both ends with matched parallel termination, this one requires less output drive current. The same speed limitations apply as the AC far end only option. 2*FT < R*C << t BIT
If the signal rise time is longer than the PCB trace (or cable) round-trip delay, then termination is usually not needed. This typically happens on short buses combined with low data rates below 50MHz, or long buses with very low data rates like 5–10MHz. Otherwise, unterminated lines have reflections, and they appear as plateaus and ringing after the signal transition (edge). Even if the line is matched-terminated, the parasitic RLC parameters will still cause some weaker plateaus to
appear, so simulations and adjustments are necessary. The ringing first period that is the largest amplitude lasts for 4*FT. So, the pulse width (half clock period, or one bit of data) has to be at least 2 to 10 times that, meaning the pulse width has to be 8 to 40 times the flight time for these schemes to work, except the full termination. For example, if the ringing period is comparable to the signal period, then we cannot damp it without damping the signal also. This applies to source series terminations with impedance-match or small value damping, as well as to parallel RC terminations. We need to run an SI simulation with estimated trace segment lengths and IBIS models, to see if any of these three cases would work in a given design, while tuning passive part parameters, or even chip drive strength if available. The goal is to maintain acceptable logic levels, monotone edges, acceptable setup time, and not too much overshoot (<0.1*VDD). Typically, less than 0.1*VDD overshoot can be ignored (“absolute maximum ratings” in a datasheet), but the acceptable limit might be even lower on space applications (satellites, space probes, spacecraft). Even these slow signals require signal integrity simulations because we use the less perfect terminations schemes. As parallel 50 Ohms cannot be used on them; the voltage is too high and current too low for parallel termination. If it cannot be made to work on a given design with component value changes, then the trace length has to be reduced, the data rate has to be lowered, or the I/O buffer type and termination scheme have to be changed to parallel far end type with differential signaling. For the non-ideal types of terminations, like damping, and AC parallel far end termination, there is a limit to their usability, their frequency, and their trace length, depending on the situation. This is demonstrated in Figure 2.4. There are several topologies used on different I/O standards, including point-to-point, balanced tree or balanced Tee, daisy-chain, fly-by, multi-drop, or multi-point, as shown in Figure 2.5. It depends on how many devices are on the bus as to how the signal propagates to one device versus to another device through definable transmission line segments, one after another or all at once, at what point the signal is terminated. Some can be used as unidirectional only, others can be used as bi-directional when the driver/receiver role swaps as part of the communications protocol.
FIGURE 2.4 AC-termination effect depending on signal speed and bus length, mid-bus waveforms in Ltspice.
FIGURE 2.5 Bus topologies.
Multi-drop or multi-point buses, where one device is driving data onto the bus and multiple devices are listening to it along the line, have to be designed in a way that all devices can see a good signal waveform. A daisy-chain interface would mean that the output of one device is connected to the input of another device and its output to the following device. Basically, multi-drop or multi-point is a parallel connection in the schematic, while daisy-chain is serial. Sometimes people call a multi-point bus a daisy chain if they are routed on the board layout device to device without branches or splits. There are many common CMOS implementations, like PCI, SPI, VME, and LPC buses. CMOS was originally not designed for terminations, with its high voltage and low current outputs, so we can only attach weak types of terminations like damping, or parallel AC. Unless we use low voltage CMOS, at 1.8V we need 24mA drive, at 1.5V a 16mA driver might be suitable to drive impedance matched parallel terminations. Unterminated CMOS buses can cause the mid-bus devices to see a two-step waveform with a plateau due to round-trip delay, basically the signal lingering near the logic level threshold for a long time. We can see this plateau on a LTSPICE simulation in Figure 2.6. It might also cause metastability in the mid-bus devices. We have to keep the plateau away from the logic thresholds, and short to improve setup timing, by experimenting with source series and far end AC termination component values and bus length (system design) in an SI simulation. For timing analysis, the flight time seen by mid-bus devices is not based on direct routing distance, but it is based on round-trip reflected-wave delay, up to twice as much as far end devices see, unless we terminate it well. If our design is not multi-drop/point, rather pointto-point, like reference clocks, then the plateau issues can be ignored. For example, if there is only one receiver, then the plateau seen half-way on the trace will not cause any issues to the only far end receiver.
Multi-drop buses have only one driver and many receivers. On a multi-point bus any device can drive the bus, they are all bi-directional. In this case we need impedance matched parallel termination at both ends of the line if running too fast or the bus is too long. It is also necessary to route the bus as a single linear trace, without branches, so we have only two ends to terminate.
What Termination Types Should We Use
• Above about 150MHz on short buses, and above 40MHz on long buses, only parallel far end termination works, but it works only with high-current low-voltage I/O buffers.
• Source series termination with far end parallel termination is suitable only for differential singling, not for CMOS, due to the voltage divider effect.
• The “no-termination” setup can be used if the signal rise time is slow, and the trace flight time is short. 2*FT < t RISE
• We can use different combinations of these schemes, for example, source AC parallel, and far end parallel Thevenin all in the same time, or source damping with AC parallel at far
2.6 CMOS Multi-drop bus example, LTspice simulation.
FIGURE
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against your pal, so that if necessary Martin can chip bits off you both with that gun o’ his.”
“I won’t do anything of the kind,” replied Jack, pluckily, although he had an uncomfortable feeling that Hegan’s revolver was pointed at the pit of his stomach.
“Guess you will,” said Hegan, sneeringly, as he stepped back a few feet. “I’m going to count three. If you ain’t makin’ yourself scarce in that vicinity by the time I say ‘three,’ I’ll fire past you. I don’t want to do any killin’, mind. I’ll fire to miss you the first time, but the second shot won’t miss.”
Jack stared stubbornly at the man, who, however, showed no signs of wavering. And the shining weapon in his hand was a painfully conclusive argument.
“One!” said Hegan.
Jack set his lips tightly but continued to hold on to the wheel.
“Two!”
“Three!”
There was a sharp report, and a bullet whizzed within a foot of Jack’s head. It would have been sheer suicide to hold out any longer against such odds. The boy frowned and walked forward to where Rod was standing.
“Of course, if you’re going to do that sort of thing,” he said, “you can have your own way just now. But you’ll have to smart for it later on.”
Taking possession of the wheel, Hegan steered farther into the bewildering fog.
“Don’t mind them, Martin,” he said. “But keep your eyes skinned, all the same, or they’ll slip one over on you.”
Although Jack had found discretion the better part of valor, he was by no means inclined to take his medicine lying down.
“You bet we will!” he declared truculently “I was an idiot to let you come off with us, anyway! It was one of you two who tried to choke me in the cabin a little while back. I felt pretty certain of it all along. But after what the watchman told me yesterday I thought I must have been mistaken.”
“I guess you’re right,” said Hegan. “My friend Martin was to blame for that. He always makes a mess of things if I’m not along to help him.”
Martin’s revolver went off, and Rod, who had again stooped quickly to pick up a belaying-pin, straightened himself with a jerk.
“Aw, would you!” grinned Martin. “Next time you try any of that stuff you’ll get hit; see?”
“What on earth do you chaps want?” Jack asked savagely. “You can’t get away with this sloop! I’ll have the fishermen hunting all along the coast for it.”
The two men exchanged glances, and Hegan winked at his companion.
“Wouldn’t they like to know?” he jeered.
“Keep your mouth shut,” Martin growled warningly.
CHAPTER XVI
CAST ADRIFT
Whatever the intention of the two men was, their plans were now being affected by something they had not anticipated. The fog had blotted out everything except a comparatively small space of the ocean around them; and, to complicate matters still more, the sails of the Sea-Lark, after flapping lazily for a while, now began to hang limply. The faint breeze had died down entirely, and the sloop lay motionless.
“This ain’t no good!” Hegan commented at length, addressing his companion. “Better set them two adrift in their dinghy.”
“What do you want to do that for?” demanded the captain, heatedly. So long as he had both feet on the sloop’s deck he stood at least some chance of defending his property.
“Don’t ask questions,” snapped Hegan. “Hop over the side, there.”
With both Martin and Hegan covering them with revolvers, the lads had no alternative but to obey. They were in the dinghy and Martin still held the painter in his hand ready to cast it loose, when an idea occurred to Hegan.
“Pass me up those oars,” he ordered.
Jack gave a sudden tug on the painter but did not succeed in dragging it from Martin’s hand.
“Come down and get them yourself if you’re so anxious for the things,” Jack retorted.
“You young varmint! Bound to give us as much trouble as you can, ain’t you?” snarled Hegan, clambering over the side and nearly swamping the little dinghy—which was never made to hold more than two—as he gained possession of the oars.
“What did you expect me to do?” asked Jack. “Hand them up to you politely and then kiss you good-by? I suppose you fellows both know you’ll go to prison for this as soon as the police put their hands on you.”
“They’ve got to catch us first,” grunted Hegan as, with his foot on the prow of the dinghy, he pushed it off. It slid a few yards through the water and then lay still by the side of the Sea-Lark until a faint puff of wind fluttered the sails of the sloop and she drifted half a cable’s length farther away.
“What in the name of goodness do you suppose those chaps did that for?” Jack exclaimed presently.
“They’ve got some crazy notion of stealing the sloop, I guess,” replied Rodney. “It is crazy, though. To begin with, they can’t get far. They’ll have to put in at Baymouth or some other place within a few miles. And when we land it won’t be half an hour before all the police along this part of the coast are looking out for them. They can’t disguise her, and they won’t have more than a few hours to sell her.”
“I can’t help thinking the same way that you do about it,” replied Jack, laughing, for in spite of the unpleasantness of their position there was something utterly ludicrous and unexpected about it. “But we’re not ashore yet. Got no oars, remember.”
“How far is the coast from here?”
Jack shrugged.
“A couple of miles, perhaps. I guess it can’t be much more. I think it lies over there,” he said, pointing vaguely into the bewildering mass of fog.
“I think it’s over here,” declared Rod, pointing in nearly the opposite direction. “The sloop is—” He turned to glance in the direction of the sloop, but found the mist had swallowed her up.
“She’s over there,” said Jack.
“No, she’s over there,” Rod contradicted.
“What are you going by? The wind, or the sun?”
“Guesswork,” owned Rod, realizing that in a dead calm, surrounded by fog, all points of the compass looked alike.
“We’re stuck! That’s all there is to it,” said Jack. “Nothing much can happen to us, though, as it’s such fine weather, barring the fog. And that’s bound to lift soon. We can paddle ashore with our hands, on a pinch, as soon as we can see where we are.”
But the fog continued to hang over the surface like a pall, and the boys waited with what patience they could muster, because, though by paddling with their hands they might be able to send the dinghy through the water at the rate of a mile an hour or even more, they were as likely as not to paddle her farther out to sea.
Suddenly Jack straightened up and put his head on one side, listening.
“What was that?” he asked.
“Didn’t hear a thing,” replied Rod.
“I did, though,” declared the captain. “Listen!”
After a while a faint creaking sound came over the water.
“Hear it then?” Jack asked.
The other nodded. “What was it?” he queried, straining his ears afresh.
A smile came slowly to Jack’s face.
“I believe it’s the sloop,” he declared. “She’s stuck, anyway, the same as we are, you know. Hegan and his pal will have to stay just where they are until a breeze happens along. And there hasn’t been more than a breath of air since they threw us out.”
“It might be some other boat,” Rod suggested.
“We’ll soon settle that,” said Jack. “Ahoy, there! Ahoy!”
He knew that call must travel some distance in such still air, and when no answering hail was returned his suspicions were confirmed.
“Can’t you picture them, as mad as a couple of hornets!” Jack chuckled. “They’ve fallen into their own trap and they can’t get out of it until a breeze comes.”
“I suppose there’s no chance of paddling back alongside and catching them off their guard?” Rod suggested.
The captain frowned thoughtfully.
“I guess not,” he said. “They’ll be getting the jumps soon. We’d make a pretty good target, remember, if they started to take potshots at us. All the same, I’m game if you are. It would be better than sitting here and doing nothing. There she goes again! You heard? It’s the boom swinging in the swell. Here, what idiots we are!” he went on, stooping and lifting the floor boards of the dinghy. “What could you want better than these for paddles? Quietly, now! If they hear us coming we shall have no better chance than when we drifted away. I expect it will be no good, anyway, but I can’t sit still doing nothing, much longer.”
Judging as accurately as possible the direction of the sound that came across the water occasionally, they began to paddle softly, and within five minutes Jack held up a warning hand and pointed ahead, where the shape of the Sea-Lark loomed dimly.
For another twenty fathoms they urged the dinghy along, until it was possible to see the sloop distinctly. Contrary to Jack’s expectation, there was nobody visible on deck. In such a dead calm it would have been useless for Hegan to stand by the wheel, but Jack was puzzled. The dinghy was now drawing near the vessel.
“I wonder if they’ve—” Rod began in a whisper; whereupon Jack silenced him with an imperative gesture. The sloop looked as though she had been abandoned, but as there was no small boat in which the men could leave her, that was obviously not the explanation. By signs only did Jack now communicate with his friend. Like a wraith, the dinghy slid under the Sea-Lark’s bow. Motioning Rod to keep the little craft from bumping against the side of the sloop, Jack placed his hands on the deck and slowly drew himself up until he was aboard the Sea-Lark again, on his hands and knees. Still nobody challenged
him. His pulse was beating a shade faster than usual as he crawled cautiously down the little alleyway between the deck-house and the low rail, for there was no disguising the fact that he was inviting trouble. There were two armed men, evidently entirely unscrupulous fellows, to contend with. If they suddenly saw him creeping along the deck, it was the most likely thing in the world that one of them would blaze away with his revolver.
Jack came near to the port-hole let into the side of the deckhouse. By looking through there he would be able to see the inside of the cabin. But unfortunately those inside the cabin stood an equally good chance of seeing him, with consequences distinctly unpleasant, if not painful. He could hear them now. They were evidently engaged in some dispute, for Hegan’s raucous voice was raised in protest more than once, and he heard Martin say: “Well, hurry up, then.”
There came, also, a peculiar sound as of dull blows and the straining of woodwork.
A wild hope had come into Jack’s head, but in order to execute the plan which he hastily formed it became necessary for him to pass before the port-hole.
Cautiously he leaned forward until his eyes fell on the forms of the men inside. They had their backs turned toward him, and were intent on some work of destruction In his hand Hegan held a short bar of steel, just such an implement as Jack had found on the cabin floor after the midnight struggle. With it he was tearing away one of the boards that formed the sheathing of the cabin. Several such boards had already been ripped off and lay in splinters on the floor.
“I tell you it’s gone!” Martin exclaimed in an angry voice.
“And if it’s gone,” retorted Hegan, turning toward his companion, with the bar of steel held menacingly in the air, “there’s only one person who could have taken it.”
“What d’you mean?” demanded Martin.
“I mean just what I say. If you’ve double-crossed me you won’t get away with it. You’ll have me to reckon with. I know now why you
didn’t want to come off in the sloop to-day I thought at first it was just because you were naturally scared o’ anything bigger than a chicken. Now I got you!”
“I tell you I don’t know a thing about it,” Martin protested in whining tones. “Maybe it’s there, after all. Smash another board off.”
Hegan returned to his task, and for a few minutes there was no sound beyond the rending of planks from the side of the cabin, and the creaking of rusted nails.
Suddenly Hegan gave a cry and put his hand down behind the sheathing.
“I see it!” he cried exultantly. “Just like we left it, too! Sort of misjudged you, didn’t I? Guess you wouldn’t have the pluck to double-cross a feller like me, though! Here it is, safe and sound!”
Then he drew from behind the sheathing the thing for which he had been seeking.
And Jack, watching through the port, saw the man’s hand grasping the strange object of his search.
CHAPTER XVII TRAPPED!
Jack had remained motionless, watching this strange spectacle, but he now crept noiselessly astern while the men were engaged with their discovery. Evidently they did not notice his form pass the port-hole, but the most critical part of his task lay ahead. If only he could reach the cockpit unobserved and fasten Hegan and Martin up in the cabin, the tables would, indeed, be turned.
The lad peered cautiously round the after end of the deck-house and his face brightened, for one of the doors was half closed. That gave him a chance to approach the companionway without being seen. His movements, however, had to be slow, for any sudden jerk on the part of the sloop would instantly have aroused the suspicion of the men. He hardly breathed as he put one foot over the edge of the cockpit and upon the broad seat, his eyes glued the while on the doors, which swung outward. There was a bare chance that he might bang both of them to and fasten them before Hegan and Martin had time to interfere. It would be the work of an instant only, once he got near enough to accomplish his object, and the catch with which the closed doors could be fastened together was hanging down temptingly.
A fresh dispute had evidently arisen between the two men, for they were speaking angrily once more, and while they were so engaged the boy gently closed the half-open door. Then with a swift movement he reached across for the other door and closed it with a bang, snapping the catch across firmly.
Instantly an outcry arose in the cabin.
“Who’s there?” shouted Martin.
“Open that door!” yelled Hegan.
For answer Jack took a key from his pocket, slipped the padlock through the catch, and locked it.
“Come on, Rod,” he called, springing back on deck from the cockpit and taking the dinghy’s painter aboard. “We’ve got them!”
“What? How did you do it?” Rod asked, puzzled. His nerves had been sorely tried by an anxious wait of fully five minutes during which time anything might have happened at any moment.
“I shut the door on them, that’s all. They were asleep at the switch!”
“Hello, there! Open this door!” the two men were now shouting together.
“You stop where you are, and be quiet,” Jack shouted back.
“Listen to me,” Hegan called out. “What’s the idea of fastening us up? Can’t you take a joke?”
“Oh, yes,” said Jack. “Now it’s your turn.”
“Well, this ain’t funny,” replied Hegan. “Just you open the door, an’ we’ll call it quits.”
“Not likely,” said the boy. “I’ll open the door when we get back to Greenport and there’s a police officer to talk to you as you come out. Perhaps you can explain to him what you mean by turning me off my boat and smashing my cabin up.”
“If you don’t let us out I’ll break the door open and then you’ll have real trouble on your hands!”
“They’ll have some difficulty in breaking that door open,” said Rodney. “Meanwhile, look at that!” He pointed to the canvas which was again fluttering. “Pretty soon we’ll be able to sail back.”
“Not till this fog lifts,” replied Jack. “I’ve got a compass, but it’s in the locker down there. There she comes,” he added as a puff of wind swept over the sea. “This’ll soon blow the fog away.”
The men below had been quiet for a few moments, evidently holding a council of war.
“Jack,” Hegan called out at last.
“What do you want?”
“I want you to open this door and have a talk.”
“You can talk where you are if you want to. I’m listening.”
“Yes, but I want to get out.”
“I have told you I’m not going to let you out.”
“If you don’t, it’ll be your funeral,” declared Hegan. “Listen here, we made up our minds that we weren’t going to hurt any one if we could help it.”
“Well, you’re not hurting any one,” retorted Jack, with a laugh.
“We will if we start shooting. We’ve got plenty of cartridges left and they’ll go clean through this door. One of you may get killed, so I’m giving you fair warning.”
“I’m willing to take a chance,” replied Jack, moving from the companionway door, and seeking safety on deck. “You blaze away if it amuses you.”
Immediately there came a muffled report from the interior of the cabin, and a bullet piercing the woodwork, sang its way over the stern of the sloop.
“Now, will you let us out?” Hegan demanded.
“Yes, very soon,” replied Jack. “We’ll be in Greenport before long.”
Another shot rang out, and Jack, who had taken hold of the wheel, gave a start as the bullet narrowly missed him. The breeze was freshening rapidly, and already he could dimly make out a portion of the coast-line, which gave the captain a general idea in which direction to steer. But to stand there and deliberately present himself as a target for the two ruffians in the cabin, had no appeal for him whatever. He slipped behind the wheel, and crouched down as low as possible, at the same time motioning Rodney to go forward, out of range.
“Don’t take any chances, Rod,” he advised.
The Sea-Lark was now leaning over gently before the breeze, and beginning to cut along slowly toward the harbor.
“They couldn’t hit a hay-stack in a passage,” shouted Rodney, derisively, as he skipped into the bow.
Immediately a shot came flying through the forward end of the deck-house, and Rodney ducked behind the mast.
“Have you two had enough of it yet?” Hegan bawled.
“Keep her going, if it amuses you,” replied Jack from his vantageground. “The more shots you fire now, the better I like it. All these holes in the side of the cabin will make the evidence against you lots worse.”
“Don’t be an idiot,” said Hegan. “You’re only making it worse for yourselves when I get at you. I’m going to shoot the lock off if you don’t unfasten it, but I’ll keep a shot for you.”
Jack knew well enough that this would prove no idle threat if the men did succeed in blowing the fastening off the door, and they would be able to do that easily enough if their ammunition held out. Still, it was something to be forewarned.
“Rod!” he called out, beckoning with his finger.
Rodney quickly came aft.
“I want you to take this wheel,” Jack said. “Keep down as much as you can and they’ll never hit you.”
“What are you going to do?”
“I’m going to get ready with the boat-hook, in case they manage to break the door open,” replied the other, grimly, as another shot came through the side of the cabin and buried itself in the woodwork of the cockpit. “See, they’ve started to fire around the lock. It won’t hold forever under that sort of treatment. If only we could keep them there another half-hour we should be round the end of the breakwater, but I’m afraid they’ll smash their way out before that.”
“You stick to the steering,” said Rodney. “I’ll tackle them with the boat-hook.”
“If you don’t do as I tell you,” said the captain, firmly, “I’ll swing her up into the wind, and we’ll lose time. Ouch!” he added, as another bullet whizzed past.
Reluctantly Rodney obeyed. Jack seized the boat-hook, and stood on the deck at the edge of the cockpit, ready for the struggle which he now felt was inevitable. It would still have been possible for him and his chum to get away in the dinghy, but the sloop was heading for harbor, and there was a tempting sporting chance for Jack to win out. Moreover, he was by no means sure that if he and Rodney did get away in the dinghy Hegan and his confederate would allow them to escape scot-free, for the men could overtake the dinghy rapidly, now that a fresh breeze was filling the sails.
Two more shots rang out, and the door of the companionway became badly splintered.
“Are you going to let us out?” demanded Hegan’s voice, in menacing tones.
Jack cautiously moved out of the way before replying.
“No, and if you put your head out you’ll get the boat-hook on top of it!” he shouted.
There was a brief pause, and then a heavy thumping began on the inside of the door. The men were using the table as a battering-ram. Jack moved nearer the cockpit again, and stood watching with misgiving the effects of the resounding blows. Suddenly Rodney gave a startled cry, at the same time pointing ahead.
Round the end of the breakwater, with all sails set, a fishingschooner was coming.
“Starboard a bit, Rod, and cut her off,” said Jack. “Hegan, you’d better stop that now,” he added, raising his voice. “There’s a schooner coming.”
This information was apparently far from good news to the two captives. The battering ceased momentarily, and three shots were fired in rapid succession at the lock, which almost broke away. When the shots ceased Jack leaped down into the cockpit, with the boat-
hook raised above his head, ready to defend himself as the men broke out of the cabin, but the instant he landed in front of the door another bullet tore its way through the woodwork, and he felt a sharp, stinging pain in his leg, just above the knee. With an involuntary cry he clapped his hand to the injured place.
“Come and take the wheel,” cried Rodney. “You’ve been hit, haven’t you?”
“Stop where you are. It’s nothing,” replied Jack, gritting his teeth nevertheless as his leg began to throb. The boat-hook was but an indifferent weapon against men with loaded revolvers, but it seemed to Jack that the enemy would have only a few shots left, if any. The sloop and the schooner, moreover, were now approaching each other rapidly. The fishing-vessel had gone about, and her present course was taking her almost straight toward the Sea-Lark. Another minute or so would bring the vessels within speaking distance. Rod was already signaling as best he could.
Below deck, the prisoners were again assailing the door, and blows fell with telling effect against the weakening lock. With poised boat-hook, Jack watched and waited. Suddenly, with a crash, the doors flew open and Hegan, his face contorted with rage, leaped up the steps.
“Drop that boat-hook!” he commanded savagely, his revolver pointing at Jack’s breast. Behind him, Martin peered across his shoulder, his features set in a malicious grin.
Jack, backing away, pointed to the schooner “You’re too late, Hegan,” he said.
“You’re too late, Hegan,” he said
Hegan shot a quick glance over the water and then, with a snarl of rage, hurled his revolver straight at the boy’s face. Jack ducked, but not in time to escape a glancing blow on the top of the head, which sent him reeling back. Seizing his advantage, Hegan leaped forward, but Rodney with a final hail to the schooner, now close at hand, left the wheel and hurled himself on top of Hegan. His weight bore the man down, and Jack, recovering, steadied himself to meet a new onslaught which came from Martin. Clutching the barrel of his empty weapon, Martin aimed a blow, but Jack was before him and brought the boat-hook crashing down on the man’s arm. The revolver dropped to the floor of the cockpit just as a deep voice came from the deck of the fishing-craft.
“Hello, there! Hello, there! What’s all this about?” It was Bob Sennet who spoke, and with flopping sails the Ellen E. Hanks nosed alongside the Sea-Lark, and the skipper, his huge hands bunched formidably, leaped to the deck of the sloop.
“You’re just in time, Captain,” growled Hegan. “These young ruffians were nearly killing the pair of us.”
Bob Sennet’s eyes fell on the dark mark on Jack’s trousers, which were already badly stained from his wound. From there his gaze traveled to the revolver at Martin’s feet. Jack, now that the worst of the excitement was over, was feeling curiously weak. He sank down on the cockpit seat, and hoped fervently that he was not going to do anything so foolish as faint. It was as though a red-hot iron was being bored into his leg, and he felt absurdly dizzy.
“Give me that gun,” the fisherman demanded of Martin, who picked up the weapon and handed it over.
Hegan made a movement in the direction of the dinghy, whereupon Bob Sennet strode forward, took him by the collar, and flung him roughly into the bottom of the cockpit.
“So these two boys were nearly killing the pair of you, were they!” the burly fisherman said. “I’ve seen one of ’em at the wheel for the last five minutes. The other has a boat-hook in his hand, and a bullet in his leg, if I’m not mistaken. That yarn don’t go with me, and it won’t
go with the police. Have they another gun, Jack?” he demanded suddenly.
“They had, but Hegan threw it at me when it was empty, and it must have gone overboard.”
“What’s their game?”
“I don’t quite know, Captain Sennet,” replied Jack, “but I’d be very much obliged if you’d help us back to Greenport.”
“You bet I will! Now, then, you two,” he went on addressing Hegan and Martin, “get onto the schooner. Nearly killing the pair of you, were they? A fine yarn! Hey! What in thunder!” Captain Sennet’s head went forward and his eyes widened in astonishment as he saw the broken, bullet-torn doors of the companion way. “Has somebody gone crazy!” he added.
Jack was by now in a state of semi-collapse, and the fisherman, picking him up, laid him gently on the deck of the sloop.
“They turned us adrift in the dory,” Rodney explained, “but there wasn’t any wind, so we were able to paddle alongside again and Jack slipped aboard and fastened them up in the cabin.”
“Well, I dunno,” said Captain Sennet, “but by rights you two ought both to be dead now, ’cording to what’s been going on. Joe,” he called out, raising his voice and addressing the mate on board the schooner, “tie those two beauties up good and tight, or they might get away from you yet. Now pass a line aboard here, and beat it back to the harbor.”
In a few minutes the schooner was heading for Greenport, with the Sea-Lark in tow, and Captain Sennet was standing, amazed, amid the scene of wreckage in this little cabin of the sloop.
“Say!” He pushed his cap back and rubbed his head perplexedly, addressing Rodney “For the love of Mike, will you just tell me what them fellers have been up to in here? Half the sheathing is torn down! They must ha’ gone clean crazy. Why—” Suddenly he stopped and his jaw dropped, as, turning round and glancing on to one of the bunks, he saw something which took away his breath.
“What in thunder!” he began; and then, with a broad smile he leaned over the bunk and fingered his discovery.
“Money!” exclaimed Rodney
“Some one must ha’ been robbing a bank!” laughed Captain Sennet. “Fives—tens—twenties! Ho, ho! I reckon that accounts for some o’ the milk in this particular cocoanut. Let’s put it in that thing,” he went on, picking up a canvas bag and stowing the pile of paper currency and coins into it. “Guess I’ll take charge o’ this till we find whose it is,” he added, dropping the bag into his pocket.
Back on deck, he gave his attention to Jack.
“We’ll have you in a doctor’s hands soon,” he said. “Much pain?”
“Not too much,” said Jack, with a grimace. “My head hurts most. I don’t think the bullet wound amounts to much.”
“Let’s have a look at it,” said the fisherman, rolling up the boy’s trouser leg and displaying a clean wound in the flesh about four inches above the knee. The bullet had entered the flesh at the front and passed out again at the back without touching the bone. Rodney produced a handkerchief, and the skipper bathed the injury with seawater.
“Never mind if it smarts a bit,” he said. “You want it clean, anyway. There’s no great harm done there, though it’s a mystery to me how you both got off as lightly as you did, with all that lead flying around.
“Had you got any money hidden in that cabin o’ yours, Jack?” he asked, after binding up the wound with the handkerchief.
“Money?” the lad asked. “There was about eighty cents in my coat pocket. That’s all I know of.”
“I mean a pile o’ money.”
“A pile?” asked the captain of the Sea-Lark. “I know there wasn’t any other money in the place. I ought to know.”
“That’s just what you didn’t know,” replied the fisherman. “I think I begin to understand it, though. You’ve seen that mess those fellers have made o’ the inside o’ the cabin?”
“I saw that through the port-hole.”
Captain Sennet drew the canvas bag from his pocket.
“This must ha’ been what they were after,” he said. He held it out and Jack examined it curiously. On its side was printed “Barker and Holden.”
“I don’t understand,” said the boy, opening the bag, and looking in puzzlement at the bills and coin within.
“You don’t know anything about it, do you, Rod?”
“Never saw it before in my life,” answered Rodney, blankly. “Whose is it?”
“I don’t know,” said Jack. “I don’t understand it at all!”
“No, nor me, neither,” said the fisherman. “Leastwise, I ain’t got the proper hang of it, but I’ve got a notion, just the same. You say these two men set you adrift in the dinghy?”
Jack nodded.
“And then as soon as your backs were turned they started to strip off all the sheathing o’ the cabin?”
“Why, yes. And I saw Hegan put his hand behind one of the boards and lift this bag out.”
“Then,” declared Captain Sennet, logically, “if they went after this they must ha’ knowed it was there, and if they did they must ha’ been the ones who put it there! Who else could ha’ knowed where it was, besides them as put it there?”
Jack sat up suddenly, with a most astounding idea in his head. “I’m going to count it,” he announced.
“Count it, eh?” said Bob Sennet. “All right. Might as well know what we’ve got.”
Eagerly Jack emptied the contents of the sack upon the seat and, with the others watching curiously, counted bills and coins. At last, “Twelve hundred and forty dollars!” he cried excitedly. “Just what I suspected! Don’t you see, Captain?”
Bob Sennet shook his head. “Can’t say I do, Jack. Guess you’d better tell me.”
“Why—why, this is the money my father was robbed of three years ago!”
“What!” exclaimed Rodney. “But how did it get here?”
“I don’t know, but—”
“I do,” interrupted the captain of the Ellen E. Hanks. “Those sculpins put it here.”
“But—but when? The Sea-Lark’s been lying over on the dunes for two years or more!”
“Well, what of it?” asked Bob Sennet. “Wasn’t nothing to keep them from going over there and dropping the bag behind the cabin sheathing, was there? If they wanted to hide it that was a pretty good place, wasn’t it? And—why, look here, Jack, maybe these fellows is the ones that stole the money from your father!”
“I wonder!” said Jack. “Anyway, it’s all a puzzle to me. Why should the men have hidden it on the Sea-Lark? And if they did hide it there, why didn’t they take it away again during all the time the sloop lay on the dunes?”
Bob Sennet shook his head in perplexity. “Now’s the time to find out, if it ever is to be found out,” he said as the schooner’s sails dropped and she sidled toward her usual berth, much to the surprise of those who had seen her put to sea a short time before.
“What’s amiss?” Cap’n Crumbie shouted from Garnett and Sayer’s wharf, seeing the sloop towing astern and Bob Sennet aboard of her.
“Telephone to the police station,” replied Captain Sennet, “and tell the chief he’s wanted down here, quick. I want to get off to sea as soon as I can.”
The watchman delivered the message, and shortly afterward the chief stepped on board the Ellen E. Hanks, where the crew were standing expectantly in a group. Jack, limping painfully, had joined
