Pipelined Diagonal Matrix Code Encoder/Decoder for 5G/6G Systems

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 06 | Jun 2026 www.irjet.net p-ISSN: 2395-0072

Pipelined Diagonal Matrix Code Encoder/Decoder for 5G/6G Systems

1Dunna kiran kumar, 2Dodla Sriram, 3TankalaVijayaLaxmi, 4Kadumula Rama, 5Pandiri Hemlatha

12345Dept. of Electronics & Communication Engineering Avanthi'S St.Theressa Institute of Engineering & Technology Vizianagaram, India

Abstract-Theincreasingdataratesandstringentreliability requirementsof5Gandemerging6Gcommunicationsystems demand high-throughput and low-latency error control codingtechniques.DiagonalMatrixCodes(DMC)havegained attention due to their strong error detection and correction capabilities with moderate hardware complexity This work presents a pipelined VLSI architecture for Diagonal Matrix Code encoder and decoder tailored for 5G/6G systems. The proposed design employs parallel and pipelined processing stagestoenhancethroughputwhileminimizingcriticalpath delay. Both encoding and decoding operations are implementedusingsynthesizablehardwaremodules,enabling efficient integration into high-speed baseband processors. Performance evaluation demonstrates that the pipelined architectureachievesimprovedlatencyandhigheroperating frequency compared to non-pipelined implementations, making it suitable for next-generation wireless communicationsystemsrequiringreliableandreal-timedata transmission. Further the designs are modified with data aware adaptive activation with bypass correction logic and parity reuse for efficienthardwareutilization.

Keywords-Diagonal Matrix Code (DMC), Error Control Coding, 5G Communication Systems, 6G Wireless Networks, High-Throughput Hardware, LowLatency Systems.

1. INTRODUCTION

One of the most significant technologicalchanges in contemporarydigitalsystemsisthequick development of wireless communicationsystemsfromtheearliestcellular generationstothefifth-generation(5G)infrastructureand theexpectedsixth-generation(6G)paradigm Theshiftto5G and 6G redefines the architectural requirements of digital hardware in terms of ultra-reliability, ultra-low latency, extreme connectivity density, and real-time flexibility, in contrast to previous generational shifts that mostly concentratedonraisingpeakdatarates.Massivemachinetype communication (Mmtc), ultra-reliable low-latency communication(URLLC),andenhancedmobilebroadband (Embb)areallexpectedtobesupportedbymodernwireless networks while also meeting strict scalability and energy efficiencystandards.

The target latency for upcoming 6G systems is anticipated to drop below 100 microseconds for crucial applications like autonomous systems, remote surgery, augmentedreality,andintelligent edgecomputing. In 5G

networks, latencyrequirementshavealreadybeenlowered to the order of milliseconds. The design of on-chip inter connect topologies, integrated memory, and baseband processors is greatly impacted by these stringent latency restrictions. Data continuously passes through intricate signal processing chains in these systems, which include equalizers,precodingunits,channelestimationblocks,Fast Fourier Transform (FFT) modules, modulators, demodulators, and forward error correction engines Because each of these phases depends on intermediate buffering and temporary data storage, internal memory dependabilityisessentialtosystemperformanceasawhole.

Aggressivegrowthofsemiconductortechnology has also brought significant reliability issues. Transistor geometriesgrowmore compact as CMOS devices decrease intothe sub-micron and nano-meter regimes, whilesupply voltagesareloweredtocontrol dynamicpowerusage.The critical charge needed to change a stored logic state is decreased by these scaling patterns. Digital circuits are therefore more susceptible to transitory disruptions such electromagnetic interference, voltage noise, temperature fluctuations, and radiation-induced Single Event Upsets (SEUs) Moreover, charge- sharing effects raise the likelihood of Multiple Bit Upsets (MBUs), in which neighbouring memory cells flip at the same time, in highdensitymemoryarrays.

Clusteredandneighbouringbiterrorshave become more common in contemporaryintegrated circuits, especially in FPGA and ASIC-based communication processors. Clustered mistakes necessitate more complex correction algorithmsthatcanrecognizeandfixseveralincorrectbits insidea singledata word,in contrast to isolated single-bit errors that canbefixedusingtraditionalHammingcodes. Sucherrorshavethepotentialtodisruptchannelestimation matrices, corrupt modulation symbols, spread throughout pipelinestages,andultimatelyraisethebiterrorrate(BER) atthesystemleveliftheyarenotfixed.

Toimprovedigitalreliability,errordetectionandcorrection (EDAC) techniqueshavebeenusedforalongtime.Singleerrorcorrectionwithlittleredundancyandstraightforward implementation is offered by traditional Hamming codes Although SEC-DED methods may detect double faults, their correction strength is still restricted. Although algebraiccodeslikeReed-SolomonandBCHprovidestrong bursterrorcorrection,theynecessitateintricatefinite-field arithmetic operations that raise latency,power

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consumption, and hardware complexity. Widely used for channelcoding,iterativedecodingschemeslikeLow-Density Parity-Check (LDPC) codes approach Shannon capacity However, because of their variable latency and high switching activity, they are not as wellsuited for realtime systems that require lightweight internal memory protection.

An internal error correcting system in 5G and 6G basebandprocessorsneedstomeetseveralrequirementsat once.Toavoidpipelinedisturbance,thecorrectionlatency must first be deterministic andconstrained. Second, highfrequency operation possibly in the hundreds of megahertz to several gigahertz rangemustbe compatible with throughput Third, in orderto address clustering and neighbouring bitupsets, repair capacity needs to go beyond single-bit errors. Fourth, to guarantee space and power efficiency, hardware implementationmustrelyon basic logic operations. Lastly, in order to accommodate expanding data pathways and changing communication standards,thearchitectureneedstobescalable.

Apotentialclassofstructuredcodesthatstrike a balance between hardware efficiencyandcorrectivecapabilitiesare matrix-basederrorcorrectioncodes.Matrixcodesimprove errorlocalizationwithoutaddingcomplicatedarithmeticby organizing data bits into two- dimensional matrices and implementing parity restrictions across several spatial dimensions.Bothverticalandhorizontalparityrelationships areusedintraditionalmatrixcodes.Thesemethodsmight, however, not be able to adequately adjust for diagonal or clusterederrorpatterns.

This idea is expanded upon by diagonal- based matrix coding, which adds parityrequirementsalongthedata matrix’ sdiagonalroutes Each data bit thus takes part in several independent parity equations in various spatial orientations. This multi-dimensional constraint structureboostsrobustnessagainstneighbouringmulti-bit mistakes and enhances error distinguishability. A 32-bit data word arrangedina4x8matrixcouldbesafeguardedby 24diagonal paritybits,allowing forthecorrectionofupto eightincorrectbitsinsidetheword,aspreviouslyshownby the Diagonal Hamming Code (DHC) architecture. When comparedtraditionalsingle-errorcorrectionsystems,thisis asignificantimprovement

Additionally, pipelining methods have been used in diagonal coding schemes to reduce combinational delay. Higheroperatingfrequenciesaremadepossiblebyreducing the critical route length by adding registers in betweentheencodinganddecodingprocesses.Even while pipelining enhances timing performance, more architectural adjustments are required to satisfy the demandsofcontemporarywireless systems for energy efficiency andstreamingcompatibility.

Because of external channel coding methods, the likelihood of mistake in internal memory or pipeline registers is typically low in high-speed communication contexts. Consequently, there is needless switching activity and an increase in dynamic power consumption whenfullcorrectionlogiciscontinuouslyactivatedforeach dataword.Reducing needless toggling is crucial for energy-efficient operation since dynamic power is proportional to switching activity, capacitance, supply voltage,andfrequency.Furthermore,simpleduplicationof parity computation circuitry causes a linear increase in hardware resources as data lengths in next- generation communicationsystemsincrease.Scalabilityisrestrictedin theabsenceoflogicsharingorhardwarereuse,especiallyin FPGAsystemswheresliceLUTsandroutingresourcesare limited

Thesefindingshighlighttheneedforanimproved diagonal matrix coding architecture that incorporates adaptive activation, balancedpipelinesegmentation,hardwarereuse, andstreaming-friendlydesignprincipleswhilemaintaining robust multi-bit correction capacity. Thus, an Adaptive Pipelined Diagonal Matrix Code architecture designed especially for 5G and 6G communication systems is proposed in this work. The suggestedsolutionuses parity reusetechniquestomaximizehardwareefficiency,selective correctiveactivationtodecrease switching activity, bypass logic tolowereffectivelatencyincommon-casescenarios, and hierarchical syndrome detectiontodiscovererror-free states early. The suggested architecture seeks to increase reliability,throughput, dynamic power consumption, and scalability for next-generation wireless infrastructures by integrating coding theory with realistic VLSI design considerations.

The suggested solution tackles the core issues of performance, energy efficiency, and dependability in contemporary communication processors by combining structured diagonal coding with adaptive pipelined architecture. In developing 5G and 6G networks, the resulting framework provides a strong basis for faulttolerant,high-speed,real-timeoperation.

2. LITERATURE SURVEY

[1] High packing densities in sophisticated FPGAs make semiconductormemoriesmoresusceptibletotemperature inducedfaults,whichcallsforeffectiveerror-detectingand correcting(EDAC)techniquesforsensitivedata.Apipelined matrix-basedEDACalgorithmbasedonHammingcodesis shown in this study. It can correct up to 6–7 random bit mistakesand8-bitbursterrorsin8-bitdata.Thesuggested design uses pipelining and optimized memory representationtoincreasecodepacewhiledecreasingarea, latency,andpower.Verilog-implemented and verified on a Zynq-7000 FPGA with Vivado 2023.2, the design surpasses current methods in terms of code and

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technology.[2] In order to decrease the execution time of instructions,thisstudyproposesavariable-lengthpipeline microcontroller design based on the RISC-V RV32IM ISA. Instructionswithoutdatadependenciescanfinishwithout needless waiting thanks to the implementation of an inorder dispatch with out-of-order writeback mechanism. With ehavior handling of multiplication and division operations to ehavior execution stages, the suggested architecture, which is based on theHummingbirdE200, allowsforvariablepipelinelengthsfordifferentinstructions. Thedesignreachesa120MHzoperationalfrequencywhen implementedinTSMC0.18μmtechnology,whichisamajor improvement over the 50 MHz Hummingbird E200 in the sameprocess.[3]Thedesignand FPGAimplementation of a multi- stage pipelined RISC-V processor utilizing System Verilog HDL are presented in this work. The processor incorporates essential modulesmemory, hazard unit, and pipeline registers for effective execution, utilizing the open-source and adaptable instruction set of RISC-V. Test benchesandModelSim–IntelFPGAEditionsimulations are used to validate the design,whichisthensynthesizedon an Altera DE1-SoC board. The suggested approach is appropriateforundergraduateVLSIdesignteachingandis consistent with contemporary processor design techniques.[4]Forreal-timeapplications,thisstudysuggests apipelinedVLSIarchitecturebased on a single MAC for the quick computation of the one-dimensional discrete wavelet transform (DWT). Using only high-pass and lowpassfilters,thedesignefficientlysharesresourcestoreduce computational complexity, and pipelining speeds up processing. Comparing the architecture to traditional parallel MAC designs, it achieves notable area and power reductions.

ItisimplementedinVerilogandrealizedonaXilinx Virtex5 FPGA. According to experimental results, the working frequencyis276 MHz with a power consumption of 200 Mw,andtheareaisreducedby44.8%andthe power savings are 31.97%.[5] A machine- learning-based design framework that adaptively modifies clock frequency based on the propagation latency of individualinstructionsisproposed in this research. The TigerMIPSprocessorincorporatesarandomforestmodelas an extra pipeline step that uses execution history, operands, and operation type as features to classify instructiondelaysinrealtime.In45nm CMOS technology, gate-level evaluationshows a 70% speedup with 30% energy reduction by coarse-grained categorization. Further performance gains of up to 89% speedup with 15.5%energysavingsareachievedusingfiner-graineddelay classification.[6] This paper describes a hardware accelerator for LU decomposition that uses two linear arrays ofprocessingenginesmappedacross differentSLR regions and is implemented on an FPGA. Block LU decomposition calculations across the PE arrays are simplifiedandeffectivelyscheduledbythesuggesteddesign. Thedesign,whenimplementedonanAlveoU50FPGA,yields an average throughput of 95 GFLOPS and a peak

performance of 128 GFLOPS. Compared to an Intel MKL implementation on a 4-core Xeon CPU, the accelerator deliversapproximately15×latencyspeedup.[7]Crosspoint resistivememoryarray-basedanaloguematrixcomputing (AMC)circuitsandthetheoreticalunderpinningsoftheAMC idea are presented in this study. To carry out essential matrix operations, such as multiplication, inversion, pseudoinverse,andeigenvectorcalculation,inasinglestep, four types of AMC circuits are shown. The use of external input, feedback settings, and methods for dealing with negative-valuedmatricesareamongthefundamentaldesign concepts covered in the study. Transfer function-based techniquesareusedtoanalyzecircuitstabilityandtemporal complexity.[8] A near memory floating-point computing architectureis presented in thisstudyfor effectivesparse matrix–vector multiplication (SpMV) in AI systems with limitedresources.Utilizingdatalocalityandmemory-level parallelism, the architecture lowers latency and boosts performance by integrating computing at the edge of memoryarrays.Thearchitectureprovideshigh-performance floating-point operations and is designed for processing sparsedatainparallel.Whencombinedwitha4KBSRAM array,thesolutionoperatesat1GHzandproducesupto370 MFLOPSwithjusta17%areaoverhead.[9]Inthisresearch,a low-latencyparallelapproachbasedontheJacobitechnique that uses CORDIC rotations to efficiently compute the eigenvalues and eigenvectors ofrealsymmetricmatricesis proposed.Reducingthe per-rotation computation time is the main contribution, which greatly lowers the parallel Jacobi method’s total latency. This approach is used to construct a highly accurate and flexible VLSI architecture thatsupportsrealskew-symmetric,complexHermitian,and complex skew-Hermitian matrices. In comparison to state-of-the-artalternatives,thedesign,whenimplemented onaZynqUltraScale+FPGA,delivers172.75MHzoperation with 43.75% reduced latency and 89.4% increased accuracy.[10]The universal VLSI architecture for calculatingmatrixinversesandpseudoinversesutilisingQR decompositionandbacksubstitutionisshowninthiswork. The suggested architecture does away with expensive division and square-foot operations by using the NewtonRaphson and CORDIC algorithms. The findings Implementationdemonstrate that the design can accommodate different matrix dimensions while still satisfying timing, resource, and real-time performance requirements. The architecture is appropriate for highperformance signal processing and control applications becauseitprovidesnear-floating-pointprecision.[11]Inthis work,GateDiffusionInput (GDI) logic is used to develop andsimulateHammingcodeencoderanddecodercircuits forlow-powerdigitalcommunicationsystems. GDI is an effective VLSI designmethodthat ehavior size,latency, andpowerconsumptionwhiledrasticallyloweringcircuit complexity. Micro wind technology is used to model and simulate the suggested designs, and the results are contrasted with traditionalCMOS-basedimplementations. Accordingtosimulation data, GDI is a better low-power designtechniquesinceitreducespowerbyover

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50% while also improving delay performance and transistor count.[12] The difficulty of creating effective error detection and repaircodesforSystemon-Chip(SoC) systemswithconstrainedmemoryandprocessingpoweris discussedinthisstudy.Inordertolowerthebiterror rate in the waterfall area, an improvedturbocodingstrategyis suggested by linking the information and parity bits of neighboringcodeblocks.Inorderto ehaviorlinklengthand regulate hardware complexity, the design restricts coupling to nearby blocks, potentially lowering electromagneticinterference.Thesuggested method works better than currentturbocodingstrategies,accordingtoa performancestudybasedonerrorratevsrepetitioncount. [13]Thisstudydescribestheconstructionofcircuitsforlow powerdigitalcommunicationthatuseCNTFETtechnologyin conjunction with inverter-based pass transistor logic to encodeanddecodeHammingcodes.Comparedtotraditional logicapproaches,thesuggestedmethodmaintainsminimal circuit complexity while providing a better trade-off between power,delay,and area.Thesuggested method is usedtodevelopencoderanddecoderarchitectures,which arethensimulatedin32nmtechnologyusingtheHSPICE tool. The advantages of the suggested design over conventional CMOS-based implementations are shown by comparative findings.[14] Convolutional encoder–decoder machinelearning modelsthat operate in the frequencydomainareusedinthisstudytoprovidealowpowerhardwarearchitectureforon-deviceaudiodenoising. Aquantizednetworkiscreatedtomaintainenhancedquality while drastically lowering memory and computational complexity by as much as 75%. A processing- element activation routing strategy is implemented to further increaseefficiency,loweringon-chipmemoryaccessenergy by3.24Μj/frameat0.65Vand18.5MHz.Whencomparedto previous efforts, the suggested chip provides the greatest PESQaudioqualityscoreandoperatesinreal-time.[15]By investigating the memory effect in atomically thin twodimensional (2D) nanomaterials, this work advances our understanding of non-volatile memory devices and their engineeringapplications.Thepaperfocusesoninnovative advancementsinmonolayermemorydevices(atomristors), where a virtual conductive point model explains how switching ehaviorresultsfromatomicvacanciesandmetal adsorption. Few-layer 2D materials, on the other hand, behavesimilarlytotraditionalconductive-bridgememory. Promising uses for these 2D atomristors include memristive devices for neuromorphic computing, nonvolatile RF switches for 5G/6G systems, and zero-power electronics.

3. EXISTING DESIGN

The Diagonal Hamming Code (DHC) architecture, which was created to enhance multi-bit error correcting capabilityinembeddedmemorysystems,isthefoundation ofthecurrentdesign. The DHC approach’s core idea is to create parity constraints along diagonal channels by

rearranging a linear data word into astructuredtwodimensionalmatrix.Incontrasttotraditionalhorizontalor vertical parity methods, the diagonal coding structure improveserrorlocalizationcapacitybytakingadvantageof spatialcorrelationsamongbitsinthematrixrepresentation. With the use of XOR-based logic, the design seeks to deliverbettermulti-bitimplementation.

A 32-bit data word is converted into a 4× 8 matrix arrangementinthisarchitecture.

The matrix representation includes geometric positioning that allows structured grouping ofbitsacross diagonaldirections,asopposedtopresenting the data as a straightforwardsequentialbitstream.Inordertomaintain spatialadjacencyrelationshipsacrossvariousorientations, each diagonal group is made up of four data bits that are chosenfromvariousrowsandcolumns.Modulo-2addition operations are used to generate three parity bits for each diagonal group. The 4 × 8 matrix contains eight of these diagonals, therefore for every 32 data bits, a total of 24 superfluous bits are created. Consequently, the encoded codeword has 56bits,resultinginacoderateofroughly 0.57.Forsimilarcorrectionstrength,thisredundancyisstill farlowerthanthatofmoreintricatealgebraiccodeslikeBCH orReed-Solomon,eventhoughitislargerthanthatofbasic SEC-DEDschemes.

TheDHCcanbeunderstoodasastructuredlinearblockcode definedoverthebinaryGaloisfieldfrom acoding-theoretic perspective. The code’s parity-check matrix is built usingdiagonal parity equations; each row of thematrix representsadistinctdiagonalconstraint.The requirement that the product of thecodewordvectorandtheparitycheckmatrixequalzeroissatisfiedbyavalidcodeword.The diagonal parity bits are recalculated and compared with the stored parity bits todeterminethesyndrome vectorduringdecoding.Thewordisdeemederror-freeifthe syndrome vector is zero. Bit inversionallowsforrepair ifthesyndromeisnon-zerosinceitspatternidentifiesthe locationsofincorrectbits.

The multi-dimensional constraint enforcement of the diagonalcodingsystemisitsstrongestpoint.Theoverlapof constraint coverage is increased since each data bit takes part in several diagonal parity equations. Multiple neighbouringfaultsimpactmultipleparityequationsatthe same time. Even in cases when errors are clustered, this overlappingactivationresultsinuniquesyndromepatterns thatenablepreciseerror localization. Up to eight incorrect bitsinside the 32-bit wordmight be fixed by thedesign. ComparedtotraditionalHamming-basedSEC-DEDmethods, which detect double faults and fix only one error, this correction strength is noticeably stronger. Even if the correcting capability has improved, there are still certain difficulties with the DHC’s hardware implementation. Combinational XOR networks, which produce diagonal parity bitsfromchosendatabits,makeupthemajorityof

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the encoder. The combinational delay of theencoderis determinedbythedepthoftheXORtrees, despite the fact that XOR logic iscomparatively straightforward and well-supportedinFPGAandASICimplementations.Aparity equation’sequivalentXORtreedeepenswithanincreasein the number of inputs, which lengthens the propagation delay. Additionally,the connectivity overhead caused by FPGA routing limitations may increase this latency. More complexity is added by the decoder architecture. All diagonal parity bits must be recalculated, a multi-bit syndromevectormustbecreated,theincorrectbitpositions mustbedetermined by interpreting the syndrome, and therelevantbitsmustbeinvertedtoremedytheproblem. These operations are cascaded within a single combinational path in a non-pipelinedimplementation. As a result, the decoder’s critical path lengthens considerably,loweringitsmaximum working frequency. Such lengthy combinational pathways limit throughput and can result in timing violations at higher clock frequencies,whichmakesthemunattractiveforhigh-speed communicationsystems.

A Pipelined Diagonal Hamming Code (PDHC) architecture waspresentedinordertoalleviatethetimingconstraintsof the non-pipelined DHC. In this version, pipeline registers were added to the encoder and decoder before and after significant logic blocks. The effective combinational delay per stage was decreased by splitting the combinational logic into manystagesthatwereseparatedbyregisters.In FPGAimplementations,thissegmentationallowedforbetter timing closure and higher clock frequency operation. Comparingtheexperimentalsynthesisresultstotheoriginal non-pipelinedarchitecture,it was shown that the critical path delay and logic power consumption were reduced. Nevertheless, pipelining did not significantlychange the corrective mechanism’s operatingbehavior, even though it increased frequencyscalability.Whetherornottherewas amistake,the correction logic continued to operate for each processed word. Because of external channel coding,theinternalbiterrorprobabilityis usually low in real-world communicationsystems. Consequently, there is needlessswitching activity when the whole corrective network is continuously activated. This staticactivation pattern helps prevent unnecessary energy loss because dynamic powerconsumptioninCMOScircuits is proportional to switching activity, capacitance, supply voltage,andclockfrequency.

Furthermore, each diagonal group’s parity generating networkswereconstructedseparatelyinthecurrentdesign.

Despitehavingasimilarstructure,thesenetworkswerenot designed with hardware reuse in mind. Consequently, redundantXORoperationsledtoanincreaseingatecountin ASIC realizations and slice LUT Consumption in FPGA implementations.Scalabilityisrestrictedbythisredundancy, especially when expanding the design to accommodate widerdatalinesthatarenecessaryforfuturecommunication standards.

The current architecture’s focus on embedded memory protectionratheronstreamingdataenvironmentsisanother drawback.Thearchitecture was not initially designed tointegrateintohigh-throughputbasebandpipelines,where deterministicone-word-per-cycleprocessingiscrucial,even if it is appropriate for memory read-write protection applications.

Inconclusion,thepipelinedversion of thecurrentDiagonal HammingCodeanditsrobustmulti-bitcorrectioncapability offerenhancedtimingperformanceandmodestredundancy. Nevertheless, there are still restrictions on streaming compatibility,adaptivecorrectivecontrol,hardwarereuse, and energy economy. The creation of an improved architecture that maintains corrective strength while meetingtheperformanceandpowerneedsofupcoming5G and 6G communication systems is driven by these limitations.

4. PROPOSED DESIGN

Whilemaintainingtheirrobustmulti-bitcorrectioncapacity, the suggested Adaptive Pipelined Diagonal Matrix Code architecture is designed to overcome the energy and performance constraints seen in the traditional Diagonal HammingCodeanditspipelinedcounterpart.Theprimary goal of the suggested architecture is to convert diagonal matrixcodingfromamemory-focuseddefencemechanism into a high-throughput, power-conscious, and streamingcompatiblearchitecturethatcanbeincorporatedinto5Gand soon-to-be 6G communication systems. The likelihood of internal data corruption is typically low in high-speed wireless communication contexts since external channel coding methods like LDPC or polar codes are present. However, the resulting clustered bit flips need to be repaireddeterministicallywithinstringenttemporallimits wheninternalerrorsarise as a result of radiation-induced disturbances,voltagefluctuations,orprocessvariances.In ordertoimproveoperatingfrequency,lowerdynamicpower consumption, and increase hardware scalability, the suggested architecture is made to retain the capacity to correctuptoeightincorrectbitsinsidea32-bitdata word.

Inthesuggestedarchitecture,theencoderrestructuresthe computationofdiagonalparityintopipelinephasesthatare balanced. The XOR networks that generate parity are dispersed among several pipeline levels rather than calculating every diagonal parity bit in a single

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combinationalblock.Themaximumpossibleclockfrequency israisedbycarefullybalancingthelogicdepthofeachstepin order to reduce the maximum combinational delay per stage.Thecriticalpathisnotdominatedbyanyonediagonal paritypaththankstothisbalancedpipelinesegmentation. Thus,thearchitecture isabletowork at high frequencies, which are characteristic of contemporary FPGA- based baseband processors and ASIC implementations in wirelessinfrastructure.Hierarchicalsyndromeevaluationis introduced by the architecture at the decoder side to increase energy efficiency. A lightweight initial detection stepdetermineswhetherthereisaparitymismatchinthe received word instead of immediately triggering full correctionlogicforeachdataword.Thecorrectioncircuitry staysdormantand the data is delivered straight to the output pipeline register when the calculated syndrome vector equals zero, whichindicatesthatthereisnoerror. Thisbypasssituationpredominatesduringregularoperation becausethelikelihoodofinternalerrorsoccurringinwelldesigned communication systems is statistically low. As a result,thecorrectionnetwork’sswitchingactivityismuch decreased,whichlowersthedynamicpowerconsumption.

Thearchitectureselectivelyengagescorrectionlogicbased onthediagonalgroupdeterminedbythesyndromepattern whenanon-zerosyndromeisfound.Onlytherectification channelcorrespondingtotheimpacteddiagonalisengaged, rather than inversion networks across all data bits. In unaffectedlogicregions,thisfocused activation prevents needless togglingandsignificantlylowersswitchingactivity. In CMOS circuits, dynamic power is related to operating frequency, capacitance, supply voltage, and switching activity. Therefore, reducing needless toggling directly increasesenergyefficiencywithoutsacrificingthroughput.

Theoptimizationofparitycomputationthroughhardware reuse is another noteworthy improvement in the suggested architecture. Conventional methods result in duplicate XOR operations since parity formulas for various diagonal groups are calculated independently. However, a thorough examination shows that diagonal equationsshareanumberofintermediateXORterms.The totalnumberofXORgatesisdecreasedbyreorganizingthe parity generating network to reuse common subexpressions. This results in less routing congestion and lower slice LUT consumption in FPGA implementations.

Reduced connection capacitance and gate count in ASIC implementations enhance area efficiency andmayresultin lowerleakagepower.

Byguaranteeingthatoneencodedordecoded 32-bit word is processed per clockcyclefollowinginitialpipelinefilling, thesuggesteddesignpreservesdeterministicperformance. The possible throughput is 32 f bits per second if the operational frequency is represented by f. In 5G and 6G systems,wherefluctuating decodinglatency isundesired, this stable and predictable throughput characteristic is especially crucial for ultra-reliable low- latency communicationscenarios.Incontrasttoiterativedecoding systems that create temporal uncertainty and necessitate numerous cycles per codeword, the suggested diagonal matrixcodearchitecturecorrectsinasinglepipelinepass.

Reliability-wise, the design maintainsthecapacitytofixup to eight incorrect bits in a 32-bit word. The likelihood of correctableerrorpatterns, given a bit error probability p,encompassesallpossiblecombinationswithuptoeight incorrect bits. In contrast to SEC-DED techniques that simply fix one issue, the reliability coverage is significantly improved. Additionally, the system’s overall power consumption is reduced by lowering switching activity through adaptive activation and bypass logic. Long-term dependability is improved by lower soft error rates, which are indirectlycausedbylowerjunction temperaturesbroughtonbylowerdynamicpowerAnother important factor in thesuggested design is scalability. By increasingmatrix dimensions whilemaintaining diagonal grouping principles, the diagonal matrixstructure can be proportionately increased ascommunicationsystemsmove towardwiderdataroutes in 6G architectures. To maintain controlled combinational depth, the balanced pipeline methodology can be expandedappropriately.Deeper pipeliningaddsmoreregisters,buttheincreasedfrequency scalabilityandenergy-delayoptimizationmakethetrade-off worthwhile. Future extensions will be feasible because hardwarecomplexityincreasesroughlylinearlywithword size.

Allthingsconsidered, the suggestedAdaptive Pipelined Diagonal Matrix Code design optimizes correction capability, operating frequency, power efficiency, and hardwareutilization in a balanced manner. In order to meet the performance and reliability needs of nextgeneration wireless communication systems, the design incorporatesstructureddiagonalcodingwithadaptivelogic control and pipeline balancing. For real-time 5G and 6G infrastructures, it converts diagonal matrixcodingfrom a static memory protection method into a dynamic, highperformance,andenergy-consciouserrorcontrolsolution.

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5. RESULTS AND DISCUSSION

ThepipelineddesignsaredevelopedinXilinxVivadotoolfor the hardware of choice is 28nm CMOS technology based Artix-7 FPGA board (xc7z020clg484-1). The system requirementsincludewindows10OS,4GBRAMinstalled withXilinxVivado2023.2.Thesimulationresultofproposed designisasshowninfig.3.

The suggested Diagonal Matrix Code (DMC)encoder anddecoderarchitecture’sproperhardwareimplementation isconfirmedbythetechnicaldiagramsproducedfollowing synthesis. The diagram shows how input ports, combinationallogicblocks,andoutputportsusedforerror correction and parity generation are connected. The synthesizeddesignmakeseffectiveuseofhardwarewith76 logic cells, 67 I/O ports, and 143 nets. The pipelined processingmethod, which lowers critical route time and increases throughput, is validated by the structured logic structure. These findings show that thesuggested architecture is appropriate for high-speed 5G/6G communication systems that need errorcontrolcoding thatisdependableandlow-latency.

Thefig.4(a),4(b)and4(c) showstechnologyschematicof theexistingandproposeddesigns.

Theperformanceof the pipelined,suggested,andcurrent DiagonalMatrixCodedesignsiscontrastedinTableX.With criticalpathdelaysof35.898nsand35.388ns,respectively, the pipelined and current implementations show comparabletimecharacteristics.Thesuggestedarchitecture, ontheotherhand,dramaticallylowersthedelayto5.791ns, demonstrating better timing performance. Additionally, power analysis reveals that the suggested design lowers overallon-chippowerusageto10.018Wasopposedto23.46 W and 23.36 W for the pipelined and current systems. Adaptiveactivationtechniques,parity

Thesuggesteddesignis bettersuitedforhigh-speed5G/6G communication systems since it exhibits lower latency, lower power consumption, and increased hardware efficiency.

Research

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Table1: Comparison Results Among Existing & ProposedDesigns

Research, 15(5), 28201–28207. https://doi.org/10.48084/etasr.12069

2. Yen, M.-H., Tsou, C.-H., Lin, T.-F., Lin, Y.-H., Ku, Y.- F., & Kao, C.-T. (2023). VLSI implementation of RISC-V MCU with a variable stage pipeline. In Proceedings of the 2023 IEEE6thInternationalConferenceonKnowledgeInnovation and Invention (ICKII) (pp. 161–165).IEEE.https://doi.org/10.1109/ICKII58656.2023.10332 786

3.Loh, S. H., Tan, G. Y., &Sim,J.J. (2025). VLSIdesign course with FPGA implementation of pipelined RISC-V processor. In Proceedings of the 2025 IEEE 15th International Conference on Control System,Computing and Engineering (ICCSCE) (pp. 36–41). IEEE.https://doi.org/10.1109/ICCSCE65566.2025.1118267 0

4. Vaithiyanathan, D., James, B. P., & Mariammal, K. (2024). A high-speed computational pipeline single MACbased VLSI architecture for real-time signal and image processing.InProceedingsofthe2024FourthInternational Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies(ICAECT)(pp.16).IEEE.https://doi.org/10.1109 /ICAECT60202.2024.10469571

6. CONCLUSION

An effective pipelined Diagonal Matrix Code (DMC) encoder and decoder architecture for fast 5G/6G communication systems was presented in this paper. To increasehardwareefficiencyandprocessingperformance, thesuggestedarchitecture uses parity reuse, data-aware adaptive activation, parallel processing, and bypass correction logic. Compared to the current and pipelined designs,thesuggestedarchitecturedramaticallydecreases the critical path delay to 5.791 ns and the overall on-chip power consumption to 10.018 W, according to implementation and synthesis data. The design is appropriate for next-generation wireless communication systems because of these enhancements, which show increasedthroughput,decreasedlatency, andoptimalhardware use.In order to offer scalable and energy-efficient solutions for ultra-high data rate 6G communicationnetworks,futureworkwillconcentrateon furtherrefiningthedesignusingsophisticated low-power approaches andoptimizedFPGA/ASICimplementations.

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