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Jpeg Image Compression Using An Fpga

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International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

Jpeg Image Compression Using An Fpga

A.Srivani1 , K.Santhoshi2 , P.Anitha3 , V.Sravya4 , Dr. S K Cheyadevi5

1,2,3,4 B-Tech Final year students, ECE department, JB Institute of Engineering and Technology, Hyderabad, Telangana 5 Head of Department, ECE Department, JB Institute of Engineering and Technology, Hyderabad, Telangana

***

Abstract - Inthisdesign,weprovideaco-architecturalstructureofJPEGimagecompressionutilizingtheFPGAplatform, whereaMicroBlaze-basedcontrolunitandanoptimizedJPEGacceleratorhavebeenused.MicroBlazeperformsthejobof system level controls such as fetching the input image file, image conversion (RGB to YCbCr), triggering the hardware accelerator,generationofJPEGheader,etc.,whileinterfacingwiththehardwaremoduleviaAXI-LiteandAXIinterconnect interface.ImagedatastoredinDDRmemorycanbefetchedthroughAXIDMAengine,whichcanperformMM2SandS2MM transferschemes.ImagedatafromthememoryisstreamedtotheJPEGacceleratorusingtheAXI-Streaminterfaceandvice versa,andalltheseprocessescanbedonewithoutrequiringintensiveprocessoreffort.

TheJPEGacceleratorhandlesthetime-consumingpartsofJPEGcompression,suchas2DDCT,quantization,zigzagscanning, andRun-LengthEncoding.Theuseofa hardware-acceleratedapproachinJPEGcompressionallowsforbetterspeedand efficiency compared to a software-only approach. In conclusion, the overall architecture takes advantage of both the advantagesofasoft-coreprocessorandthoseofahardware-accelerateddesigninordertoeffectivelycompressimagesusing JPEGalgorithmsonFPGA.

Key Words: FPGA, MicroBlaze Processor, JPEG Hardware Accelerator, AXI-Lite Interface, AXI Interconnect, GB to YCbCr Conversion,2DDCT,Quantization,ZigzagScanning,Run-LengthEncoding(RLE).

1. INTRODUCTION

Withtheemergenceofmultimediaapplications,ithasbecomeimportanttoefficientlystoreandtransmitimages.High-quality imagestake upa lot ofstorage space andrequire huge bandwidth fortransmission. Image compression techniqueshave thereforebecomeveryimportant.Amongallthecompressionstandards,JPEG(JointPhotographicExpertsGroup)hasemerged asthemostpopularimagecompressionmethodthatoffersgoodcompressionandsatisfactoryperceptualimagequality. JPEGcompressionmakesuseofhumanperceptionbychangingtheimageformatfromRGBtoYCbCr,performing2DDiscrete CosineTransformonimageblockstodecomposelow-frequencyandhigh-frequencyinformationfromimages,thenapplying quantizationandentropyencodingthroughRun-LengthEncodingandHuffmancodingmethods.Thoughtheaboveprocedure iswell-establishedforJPEG,itiscomputationallyveryexpensive,andsoftwareimplementationcannotbeusedfortime-critical applicationssuchasvideosurveillanceandmedicalimagingapplications.

TheFPGAoffersagoodsolutionbyvirtueofitsreconfigurableparallelhardwarecharacteristics,whichallowcustomized pipeliningresultinginfastexecutiontimeandlowlatency.Thismaybeachievedbyemployingahardwareandsoftwarecodesignarchitecture,wherethetasksperformedaspartofJPEGcompressionaresplitintotwoparts–onecarriedoutbythe processor,whichperformsthesystem-levelfunctionslikecontrollingthesystem,colorconversion,andgenerationofJPEG headerinfo,andtheotherbyahardwareaccelerator,whichexecutestheprocessesofDCT,Quantization,ZigzagScan,andRLE concurrently.

ThispaperpresentsahardwaredesignoftheJPEGcompressionalgorithm,whichusestheco-designarchitecture,wherea MicroblazeSoftCoreProcessorperformsthesystem-leveltaskswhilethecustomizedRTLHardwareAcceleratorexecutesthe imagecompressionoperations.AXI-LiteandAXIStreamprotocolsprovidethecommunicationmeansamongthecomponents athighspeed,whereastheemploymentofAXIDMAfacilitatesautomaticmovementofdatafromtheDDRmemorytothe hardwareaccelerator.

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

2. LITERATURE SERVEY

2.1 Introduction to Image Compression

Compressionofimageshasbecomeanabsolutenecessityincontemporarydigitalsystemsowingtothefast-growing numberof multimediaapplications.Asmoreandmoreemphasishasbeenlaidonstoringefficientlyandtransmittingquicklythevisual data,alargeamountofresearchworkhasgoneoninthisfield.InthewordsofIainRichardson[1],compressionsystemsare meantforeliminatingredundancyfromimageandvideosignalswhileensuringacceptablequalityintheresultingimageor videosignal.Redundancycanoccurinthespatial,temporal,andperceptualdomains.Efficientcompressiontechniquesmakeuse ofsuchredundancy.AsstatedbyPeterSymes[2],compressiontechniquescanbegroupedintotwobroadcategories-namely, losslessandlossy.Theformerinvolvescompressingthedatawithoutanyloss,whereasthelattermakesuseofsomedatalossin ordertoachievegreatercompressionratios.Lossycompressionispreferredinimageandvideosystemsbecauseofitsefficiency.

2.2 JPEG Compression Standard

JPEGisoneofthewidespreadstill-imagecompressionstandards,developedbytheJointPhotographicExpertsGroup(JPEG).The JPEGstandardusingtransformandentropycodingtechniqueshasbeendescribedindetailbyPennebaker&Mitchell[9].This standardwasaimedattheeffectivecompressionofcontinuous-toneimages,e.g.,photographs.TheofficialdefinitionoftheJPEG standardcanbefoundinISO/IEC10918-1[10]bytheInternationalTelecommunicationUnionandISO/IEC.Therearethree modesofoperationinthisstandard,namely,baseline(sequential),progressive,andhierarchical.However,thebaselinemodeis morepopularduetoitseffectivenessandease.JPEGcompression,basedonWatkinson[4],includescolorspaceconversion, image block segmentation, block transformation, quantization, and entropy coding. Besides, every stage contributes to minimizingthedataamountandmaintainingtheimagequality.

2.3 Transform Coding and Discrete Cosine Transform (DCT)

Transformcodingisoneofthemostimportanttechniquesforachievingimagecompression.AsperWeidongKou[6],transform codinghelpsachieveenergycompactionwherethemajorityofenergyofthesignalgetscompactedinasmallnumberoflowfrequencycoefficients.OneofthemostfrequentlyusedtransformsistheDiscreteCosineTransform,whichisutilizedinJPEG. AccordingtoNetravali&Haskell[7],theDiscreteCosineTransformisanefficientapproachforrepresentingimagedatausing cosinebasisfunctions.Byapplyingthetransform,wecaneffectivelysplittheinformationaboutthepictureintotwotypes–lowfrequencyandhigh-frequencycomponents.AsnotedbyGonzalez&Woods[3],low-frequencycomponentscontainthemajority ofvisibleinformation,whereashigh-frequencycomponentscapturetheremainingdetailsandnoise.Therefore,byfocusingon low-frequencycomponents,thetransformcodingbecomesmoreefficientandcanpreservethemostvisibleinformation.

2.4 Quantization Techniques in Compression

QuantizationisavitalpartofJPEGcompressionandrepresentsthemainreasonfordataloss.InthewordsofWatkinson[4], quantization lowers the accuracy of DCT coefficients by dividing them by certain pre-defined values of quantization and roundingdowntheseresults.Asaresult,lesscrucialdataiseliminatedfromDCTcoefficients,especiallythehigh-frequency ones.Quantizationleadstointentionalimagequalityloss,andmostlikely,apersoncannotnoticesuchdamagewiththeirown eyes.AccordingtoKou[6],theselectionofaquantizationmatrixlargelyinfluencescompressionefficiencyandimagequality itself.Thegreaterquantizationvalue,thebettercompressionandtheworsequality,whilelowquantizationleadstohigher qualityimageswithlargeramountsofdata.Thebasisofquantizationmatricesdependsonthepeculiaritiesofahumanvision system.

2.5 Entropy Coding and Data Reduction Techniques

Followingquantization,compressioncontinuesviatheapplicationofvariousentropycodingmethods.AccordingtoPennebaker &Mitchell[9],entropycodingisdescribedasalosslesscompressionmethod,takingadvantageofredundancieswithinthedata. Runsofzero-valuedcoefficientsresultingfromquantizationarecompressedusingRun-LengthEncoding(RLE).Thisisthen followedbyHuffmancodingwherethesymbolsoccurringmoreoftenareencodedwithshorterbitswhilelessfrequentsymbols areassignedlongercodes.Suchcodinghelpstogreatlyreducethesizeofthedata.Havingstatedthesignificanceofentropy codinginenhancingthecompressionprocess,Effelsberg&Steinmetz[5]stressthatentropycodingcontributessignificantly towardsefficientcompressionwithoutloss.

2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

2.6 Research Gap

SignificantadvancementshavebeenmaderegardingresearchonimagecompressionandJPEGimplementationusingFPGAto increasetheefficiencyofcompressionandimprovethespeedofprocessing.Mostoftheresearchers'effortshaveconcentrated on implementing the basics, such as Discrete Cosine Transformation, quantization, entropy encoding, and color space transformationtoenableeffectivecompression.Theaboveprincipleshavebeenadoptedsincethereexistsanidealbalance betweencompressionratioandimagequalitymakingtheJPEGcompressiontechniquequitepopular.However,despitethe above-mentioneddevelopments,afewweaknesseshaveemerged.Oneofthesignificantconstraintsthathavebeendiscoveredin thecurrentliteratureconcernsthesoftwareimplementationadoptedbyprevioussystems.Althoughsoftwareimplementation gives roomforflexibilityinimplementation,itcannotsatisfy real-time constraintssince the process ofcomputing is quite complicated

3. PROPOSED SYSTEM

ThepaperdiscussesthedesignofanFPGA-basedsystemforcompressingJPEGimagesusinghardware-softwareco- design.The keyprincipleinvolvesmergingtheprogrammablecapabilitiesofaMicroBlazesoft-coreprocessorwithparallelizablehardware accelerators.ThesecomponentsareintegratedonasingleprogrammablelogicchipoftheXilinxArtix-7series(DigilentNexys4 DDRboard).Fromtheperspectiveofsoftwaresolutions,theroleofMicroBlazeisresponsibleformanagingcontrolprocessesof theentiresystem.ThisprocessorloadstherawimagedatafromthememoryintotheDDRmodule.Then,insoftwaremode,the image is converted from the RGB to YCbCr color space because the JPEG compression process is optimized when applied individuallytoluminanceandchrominancedata.Finally,theMicroBlazeprocessorconfiguresthehardwareacceleratorusing parametersofsourceanddestinationaddressesandtransferlengthbymeansoftheAXI-Lite busprotocol.Additionally,it createsthemandatoryJPEGfileheadercontainingSOI,DQT,andDHTmarkersandinsertsitatthebeginningofthebitstream file.

RegardingthehardwarepartofJPEG,theJPEGAcceleratorwillimplementthetime-consumingprocessesofcompressionusing pipelineoperations.Firstly,atwo-dimensionaldiscretecosinetransformisperformedoneachpixelblockwithdimensions8x8 toconvertthesignalfromthespatialdomaintothefrequencydomain,allowingalmostalltheenergyoftheimagetobestoredin afewlowfrequenciescoefficients.Thenquantization,throughwhicheachobtainedDCTcoefficientisdividedbyavaluefromthe quantizationtable,roundedoffandconvertedintoaninteger,resultinginthemaindatacompressionprocess.Followingthatis zigzagscanning,inwhichthevaluesofcoefficientsarerearrangedfromlowfrequencytohighfrequenciessothatallnon-zero valuesoccupytheleadingpositions,andalargenumberofzeroesoccuratthetailofthesequence.Finally,run-lengthencoding compressesthesezerosequencesinto(run_length,value)tuples.

CommunicationwiththeprocessorandhardwareiscoordinatedthroughAXIinterconnecttechnology.TheAXI-Liteisemployed insendingcontrolsignalsandregisterread/writeoperations.TheimagedataistransferredusingAXI-Streaminterface.TheAXI Interconnectconnectsthemastersandslavesthroughalltransactionswithaddressdecodingandarbitration.TheAXIDMA controllerautomaticallytransfers the data where the raw image data istransmittedfromDDR memory to theaccelerator throughtheMM2SpathwhilesendingtheoutputimagedatatotheDDRmemoryviatheS2MMinterfacewithoutoverloading theMicroBlazeprocessor.TheDDRmemoryactsasthebuffertostoreimagesthroughouttheprocess.Overall,thereisreal-time imagecompressioninwhichthesystemachieveshighthroughputandlowlatencyalongwithFPGAresourcesoptimization. Additionally,thecompressionprocessyieldsgoodqualityofthecompressedimages.

4. METHODOLOGY / SYSTEM ARCHITECTURE

4.1 SYSTEM ARCHITECTURE

DesignArchitectureoftheSystemUnderConsiderationConsistsofThreeComponents:theMicroBlazeSoft-CoreProcessor,the HardwareEncoder/DecoderforJPEGImageFormat,andtheAXIInterconnectFabric.Suchanarrangementmakesitpossibleto designaco-processorsystemconsistingofhardwareandsoftwarecomponents,implementedintheXilinxFPGAdevice.

4.1.1

MicroBlaze Soft-Core Processor

MicroBlazeprocessorisasoft-core32-bitRISCprocessorprovidedbyXilinxCompanyandsynthesizeddirectlyintheFPGA fabric. The processor serves as the control and management processor for the whole systemand completes the following functions:readstheinputimagedatafromexternalDDRmemoryintothedatastreamofthesystem;transformstheRGBinput

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

datatotheYCbCrformatbysoftwarefunction;configureshardwareencoder/decoderthroughAXI-Literegisterwrites;issues DMAs.

4.1.2 JPEG Hardware Accelerator

JPEGhardwareacceleratorisuser-designedRTL(RegisterTransferLevel)IPcore.ItrunsonFPGA'sprogrammablelogic.The hardwareacceleratoracceptsstreamof8x8pixelsblocksusingAXI-Streambusinterface,andpassesthemthroughthepipeline, whichincludesDCTtransformation,quantization,zigzagscanningandRLEencoding.Foroptimalspeed,pipelineisoptimisedso thatRLEcompressionofone block,quantizationofsecondblock,andtransformationwithDCTofthirdblockcanbe done simultaneously,withnotimewasted.Memory-mappedregisterwithAXI-LitebusisprovidedforconfigurationofJPEGhardware accelerator.

4.1.3 AXI Interconnect and DMA

In the implementation, the ARM's AMBA (Advanced Microcontroller Bus Architecture) based AXI (Advanced eXtensible Interface)protocolsuiteisused.AXIInterconnectIPisresponsibleforconnectingtransactionsfromthemaster(MicroBlaze)and slavesconnectedtobusnetworkofdesign.AXIDMAhandlestheefficienttransferoflargeamountsofimagedatabetweenDDR memoryandstreamingportofthehardwareaccelerator,withoutprocessorintervention.MM2S(Memory-to-Stream)channel accounts for data transfer from DDR memory to JPEG hardware accelerator and S2MM (Stream-to-Memory) channel for compresseddatatransferfromhardwareacceleratortoDDRmemory.

Fig –4.1: SystemArchitecture

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

4.2 BLOCK DIAGRAM

5. RESULT AND DISCUSSIONS

Thesuggestedarchitecturewasassessedforperformance,resourceuse,andcompression.JPEGcompressionwasmuchfaster withthehardwareacceleratorthanwithsoftwareontheMicroBlazeCPU.TestingshowsthatoutsourcingDCT,quantisation, zigzagscanning,andRLEtohardwarespeedsupprocessingbyseveraltimes,allowingnear-real-timeimagecompressionfor moderate-resolution photos. AXI DMA boosts performance by transferring data quickly without CPU constraints. FPGA resources are used according to parallelism, with the accelerator using logic parts, DSP slices, and block RAM. ThehardwareimplementationmaintainsJPEGstandardeffectiveness,sincethecompressedpictureshaveacceptablevisual quality.Basedonquantisationsettings,compressionratesareequivalenttoconventionalJPEGimplementations.Thedesignof an FPGA-based JPEG compression technique based on hardware-software co-design technique has been successfully developedandtestedontheXilinxArtix-7FPGAplatform.Inthisimplementation,thedesignincorporatestheMicroBlaze processor for executing control commands, while a hardware accelerator executes all complex algorithms like the DCT, quantization,zigzagscanning,andRunLengthCoding(RLE).Theresultsshowanotableimprovementinspeedandlower latencywhencomparedtosoftwareimplementations.SinceFPGAtechnologyishighlyflexible,itprovidesefficientparalleland pipelineexecutionofallstagesinthecompressionalgorithm.Thus,byoffloadingtheDCT,quantization,zigzagscanning,and RLEfromtheprocessorandexecutingthemusinghardware,allcomputationallycomplexstageshavebeenoffloadedfromthe MicroBlazeprocessorsothatthelattercanexecutecontrolcommands.Thehardware-softwareco-designtechniqueisbuilton thisstrengthandhenceproducesimprovedresultsasevidentfromthefindings

FromthesimulationoutputsseenusingwaveformanalysisfromtoolslikeModelSimorVivado,thefunctionalityoftheRTL pipelinewasverified.Thesimulationstookplacewithinthetimeperiodof0to14milliseconds,depictingalltheeventsfrom resettingofthepipelinetothegenerationofitsoutput.Inthefirststage,thesystemremainedintheresetstatewherethe majorityofthesignaloutputswereinanuninitializedstate.Duringthesecondstagefrom1to8milliseconds,thedatasignalsfor pixelsY,Cb,andCrtoggledrapidly,representingtheprocessingofinputdatabythepipeline.Finally,duringthelaststagefrom8 to14milliseconds,theoutputsignalsforpixelsY,Cb,andCrattainedthevaluesof0xFF,0x80,and0x80respectively,thus depictingpure whitecolorinthe YCbCrcolourspace.Thiswasevidentfromtheoutputsignal ofpacked24-bitdata being 8080FF.Thecompressedimageshadgoodvisualquality,thusindicatingapropertrade-offbetweencompressionratioand performance.TheAXI-Streamwasabletohandledatatransfersthroughthepipelinebyusingcomp_tvalidandcomp_tready handshakesignalsinordertotransferthedataonlywhenbothsignalsarehighatonce.

Fig – 4.2: BlockDiagram

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

Fig – 5: (a) Imagebefore compression
Fig-5: (a) Image after compression
Fig -5: (b) Imagebeforecompression
Fig-5: (b) Imageaftercompression
Fig-5: SimulationResult

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

Table-1: Parametercomparisonofimagecompression1

6. CONCLUSION

Thispapershowsaneffective FPGA-basedhardware–software co-design methodforJPEG picture compression.Withthe flexibilityofaMicroBlazeprocessorandthehigh-performanceofaspecialisedhardwareaccelerator,thesystemimproves processingspeedwhileusingresourcesefficiently.AXI-basedcommunicationandDMA-drivendatatransferallowsoftwarehardwareintegration,decreasingprocessoroverheadandenhancingsystemperformance.Thesuggestedapproachisidealfor high-performancereal-timeimageprocessing.Futureworkmayoptimisetheacceleratorarchitecture,enablegreaterpicture resolutions,andincludecompressioncapabilitieslikeHuffmanencodingoradvancedimageformats.Tosummarize,theproject providesahigh-performancesystemforcompressingimagesinJPEGformat,designedbasedonFPGAtechnologybymeansof hardware-softwareco-design.Integrationoftheprocessorwithadedicatedhardwareacceleratorprovidesfast,low-latency, and high-throughput operations impossible to perform in case of software-only solution. The pipelining of the hardware acceleratorenablessimultaneousrunningseveralstagesofthecompressionprocessandefficientusageofresources.Usageof AXI interfaces and Direct Memory Access significantly increases system efficiency by providing reliable and processorindependent data communication. The developed system efficiently decreases processor load and provides good-quality compressedimages,thereforebeingsuitableforreal-timeapplicationsincludingmultimediaprocessing,surveillancesystems, embeddedsystems,andcommunicationsystems.Althoughithassomedrawbacksthedesignisstillveryefficientandscalable, anditcanbeemployedforefficientmodernimagecompression.Ascanbeseen,theideaofhardware-softwarecodesignshows itselftobequiteeffective,enablingthebesttrade-offbetweenthespeedofcalculations,flexibility,andefficiency.Moreover,the proposedsystemisveryflexibleandcanbemodifiedfordifferentapplications.Therefore,onecouldaddfullHuffmanencoding forfullycompliantJPEGencoding;createasimilardesignforsupportingvideocompressionupgradethedesignbyusingmore

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056

Volume: 13 Issue: 04 | Apr 2026 www.irjet.net p-ISSN: 2395-0072

advanced FPGAs for increasing the performance and diminishing the energy consumption; use the design for very highresolutionimages;andfinallyimplementadaptivealgorithmsbyusingmachinelearning.Thismakesourdesignveryattractive.

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