Design and Performance Analysis of 8 x 8 Network on Chip Router

International Research Journal of Engineering and Technology (IRJET) e ISSN: 2395 0056

Volume: 09 Issue: 06 | June 2022 www.irjet.net p ISSN: 2395 0072

Design and Performance Analysis of 8 x 8 Network on Chip Router

Preethi T S1, Jayanth K Holalkeri2 , Manasa Dev G J3 , Manoj M Biradar4 , Nagesh R Shanbhag5

1Assistant Professor, Dept. of Electronics and Communication Engineering, Sapthagiri College of Engineering, Karnataka, India

2345 Student, Dept. of Electronics and Communication Engineering, Sapthagiri College of Engineering, Karnataka, India ***

Abstract Network on chip is a new prototype model in complex system on chips that provide an effective on chip communication networks. The information is transmitted through the interconnected modules in terms of packets. The main task of router is routing the data. So, the router architecture must be efficient with lower latency and higher throughput. In this project, we design and implement a 2D Network on Chip router mesh having four ports connected to other ports in four directions, namely North,South,West,East, and the fifth connected to the Local processing element through a network interface. This project is aimed to improve “Quality of Service” by employing algorithms like wormhole, routing, arbiter and crossbar switching.

Key Words: Bandwidth reservation, Flitting, Label switching, Networks on chip, Quality of Service, Streaming applications, System on Chip.

1. INTRODUCTION

The recent technological advancements in the domain of semiconductorintegrationtechnologyistofillthenumberof workingtransistorsonanavailablechipareaforfabrication, satisfyingtheMoore’slawasshowninFig 1,whichresulted indevelopmentsoftechniquesandtechnologiesinthefield ofSystemonChip,hencethishasresultedwithnewarenato the work space of miniaturization and this has highly influenced by gate level circuit association for the Application Specific Integrated Circuit (ASIC). Then technologieshavetobedevelopedin linewiththedemands of market space and design time for execution, all these criteriaofinnovationstomeettheneedsofcommunication intheexistingdomainwhichleadthescopefortheevolving of networking on the same silicon chip for communicates leadingtotheeraofNetworkonChip

Network on chip is one such innovation known for its adaptation and flexibility of operation over the chip by satisfyingthefactorofpower,areaandnumberofgates.The ASICandSoCdesignapproachesarewellsuitedforvarious integrationofperipheralswithitsapproachesmeetingthe architecturalrequirementfortheminimizationofthedelay and effective communication among the devices in both simplexandduplexcommunicationcriteria.Thisleadstothe simplificationofvariousredundantinterconnectionsamong variousperipheralsintheconnectionplatformwhichshould befaulttolerantaswellforsuccessiveimplementationofthe desiredsystem.Butinthepresentscenario,fortheeffective on chipcommunicationdesign,SoCisthebestsuitedoption butnotfairenoughfortheeffectivecommunicationamong the peripherals. Hence, it requires reframing of the architecture to achieve minimum delay with maximum reliability, which can be obtained by interfacing NoC with SoC.

NoCbasedsystemsalsoplayavitalrolefordataexchange.To meettheneedsandrequirementsofdatahandlingoverthe different types of topology and algorithms for memory or buffer baseddatatransmissiononanFPGAdevice,itrequires DynamicallyReconfigurableNoC(DRNOC).Inthisprojectwe are bound to design a router under two dimensional structure.LaterthedesignisproposedingeneralizingtoNx N structure for the improvement of the properties of the FPGAviz,delay,throughput,LUTandflip flopsusingXilinx ISE platform for simulation and testing of the properties comparativelyovertheexistingsystems.

2. LITERATURE SURVEY

The paper [1] proposes switch model design and implementationforstudents’laboratoryactivities.Thethree staged switching architecture comprising of software and hardwaresystemswhicharebasedonmodular3x3switches, with controller as an Arduino microcontroller. The switch usesafewstagesofsmallerNxNcrossbarswitchestohelpin producing non blocking connections and forming an NxN network.Asthetiniestcomponentwithinwhichaswitching systemexists,isasquaredcross barswitch.Thisswitchhas tobedesignedinsuchawaythatitshouldbeabletoconnect all inputs to all its outputs. The blocking is due to busy destinationastheexperimentconductedalsoitshowcases 94%successfulconnectionswhile6%blockingisnotcaused duetobusyswitches,butduetobusydestinations.

Fig -1:Evolutionoftransistorintegrationonachip

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The paper [6] examines the impact of failures on the reliability of the chips and develops corelating passive counterprotocolseithertopreventorrecoverfromthem.In thisview,severalschemeswereadaptedinordertoreduce variouskindsoferrorsymptoms,whileareaandpowerareat aminimum.Overanormaltransmissionscheme,itrequiresa 3 flittingre transmissionbufferpervirtual,sinceaflitmust bekeptfor3cyclesafteritleavesthecurrentnode.Theleast complextypeoftransmissionbufferisaQueueworkingon the principle of First In First Out (FIFO) buffer [25]. Such implementationtypehasoneinputportandoneoutputport, and has a control logic. The concept of deadlock has been enormously stressed upon. Some of errors mainly encountered in the router are VC allocator error, crossbar error,handshakingerror.Theschemeturnedouttobehighly effectivebothintermsoflatencyandpowerevenunderhigh errorrates.Allofthesemechanismsdescribedinthework helps in keeping the critical path of the Network on Chip routerintact.

The work proposed in [9] describes the design of on chip routersbasedonpowerconsumedanditsareaoccupiedby chip.Proposedarchitectureofon chiprouterinthisgivesthe resultsinwhichpowerconsumptionisreducedandsilicon area is also minimized. This router for NoC increases throughput, and introduces architecture which shows an improvementinFigureofMerit.Butincreasestheareaand powerduetoextracrossbarandarbiterscheme,andgotup to94%ofthroughput,whilepowerconsumptionisincreased by the factor of 1.28. [10] This approach reduces power consumption.Italsopointsatthebufferutilizationbymaking thechannelsbidirectionalandshowsdrasticimprovementin the performance of system. A router architecture with ReliabilityAwareVirtualRouterallocatesmorememoryto thebusychannelsandlesstotheidlechannels.Thissolution isdelayefficientbutnotareaandpowerefficient.

The paper [20] presents how a NoC topology, routing algorithmandswitchingarevitalincommunication. Inany NoC architecture, routing algorithm is an important key factor. The path chosen by the packet from source to destinationisdefinedbyaroutingalgorithm.XYalgorithmis one of the simplest routing algorithms used in NOC. The paper reviews a different XY routing algorithm that is implemented.Theuseofthisalgorithmistotallydependent ontheapplicationandenvironment.Theselectionofwhich totallydependsontheapplicationandthetrafficofpacketsin the network. Because the simplicity in implementation is importantinallarchitecture,XYroutingalgorithmiswidely used. The Dynamic XY routing algorithm achieves better balanceinloaddistributionandalsoprovidesdeadlock free and livelock free facility where the user can’t compromise withaccuracyofdatareceived,theygoforthefault tolerant routinglikeXYX.Finally,wecanconcludethatthechoiceof XY routing algorithm is totally dependent upon environmentalconditionofNOCarchitecture.

The paper [14] proposed an approach to find the shortest path distance between two nodes implementing on FPGA technology.TheFPGAarticulatesparallelismtosignificantly reducestepsascomparedtosequentialeffort.Inthispaper, A* algorithm is chosen for the shortest path distance calculationbasedonitsheuristicbehaviorsinceitachieves superiortimerunning.Shortestpathalgorithmsareapplied for applications like transportation and networking. If the shortestpathiscalculatedongeneralpurposeprocessor,to read the input there are separate instructions, and then computetheresulttoproducetheoutputwhichslowsdown theoverallperformance.Theresearchworkreducesdelayin findingtheshortestpath.Thisresearch[14]contributesin finding the shortest path with reduced delay by taking advantage of parallel processing in FPGA. A new design in coprocessorimplementationisproposedusingA*algorithms technique,andusingthisbringsintheconceptofparallelism.

3. SCOPE OF WORK

Based on the literature survey and various studies, in this paperweareboundtodesignaLabelSwitchingNetworkon Chiproutercomprisingoffollowing:

1. Crossbarswitchtoestablishaconnectionfromeach inputtoeachoutput.

2. Arbitermoduletocheckportvalidityandtoflit.

3. ANoCmanagerusedforbandwidthallocation.

4. ALSrouterthatchecksiftherouterisvalidornot.

Wedesignandimplementallthemodulesmentionedabove, usingXilinxISE14.7andinstantiateitinatopmoduletoform asinglerouter.Furtherweimplementpoweroptimization techniquestoreducethepowerandimproveQoS.

4. METHODOLOGY

The following steps are carried out to form an 8x8 NoC Router.

4.1 To Design a Crossbar Switch

ACrossbarswitchisdesignedinXilinxISEasshowninFig 2.

1. Everyonchiprouterhas5portsnamely,Local,East, West,NorthandSouth.

2. Everyportneedstohaveonemultiplexer,therefore forfiveportsweneedfiveMUX.

3. Thecrossbarmodulehasseveninputportsandfive output ports and five wires for intermediate connections.

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4. The5bitenablebusisusedtoenabletheparticular MUXand3bitselectlineisusedtoconnectinputtoa particularoutput.

5. Everypossibleconditionofenableandselectlines are specified and based on that condition the incomingportsandoutputportsareconnected.

6. The select line bits are determined by the arbiter modulediscussedbelow.

4.3 To Design an NoC Manager

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AnNoCmanagerisdesignedandtheRTLschematicisshown inFig 4.

1. NoCmanagerisusedtomonitortheusedandthe unusedbandwidth.

2. Itmainlyworksontheprincipleofedgedetection.

3. Edgedetectionbetweentwocorrespondingrouters isdonebyconsideringLSBbitsasshowninFig 5

4. EveryporthasoneNoCmanager,soforfiveports there are five NoC manager present in a single router.

5. Scaling factor is set to 5 between two slots and 2 betweenthepacketsinoneslot.

6. Onlyifthebandwidthisgreaterthan2,theportis consideredtobeavailable.

Fig -2:CrossbarSwitchusingMUX

4.2 To Design an Arbiter module

An arbiter module is designed in Xilinx ISE and the RTL schematicisshowninFig 3

1. An arbiter module is designed using arbiter algorithm and it consists of 5 input ports and 6 outputports.

2. Thismodulehelpstoflitthemessagebits.

3. Based on the condition of the destination ID and label,itchecksthevalidityoftheport.

4. Inferringtheselectconditionsofallthefiveports, theoutputportisallocatedwiththeselectlinebits usedincrossbarmodule.

Fig 4:RTLSchematicofNoCmanager

Fig -5:EdgeDetectionoccurringinNoCmanager

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4.4 To Design a Label Switched Router

LabelswitchedrouterisdesignedandtheRTLschematic isshowninFig 6.

1. A label based switching router is connected to all thefiveports.

2. It also consists of a Queue module which implementsFIFOoperation.

3. Itisusedtogeneratelabelsandtocheckwhether portisvalidornot.

4. It checks whether received packet is valid or not andwhetherthepacketissuccessfullytransmitted ornot.

5. Italsocheckscongestionoftheport,iftheportisin use the packet is buffered in FIFO module and whethertheFIFOisfullornot.

Fig 7:SimulationresultsofCrossbarmodule

Fig 6:RTLSchematicofLSRouter

5. RESULTS OF THE PROJECT

5.1 Simulation of the project.

Crossbar Switch and Arbiter module are simulated and verifieditsoperationsuccessfully.Thesimulationresultsof crossbarandarbitermoduleareshowninFig 7andFig 8 respectively.

Fig 8:SimulationresultsofArbitermodule ThespecificationsforthisprojectismentionedinTable 1. Table -1: Design Specification

Once all the sub blocks are designed and verified, we instantiateallthemodulesinthetopmoduletoformasingle router.Apacketformatof22bitsisconsideredofwhich6 bitsdenotethesourceanddestinationaddress,remaining16 bitsdenotesthemessage.Thenthesinglerouterismultiplied 9 times to form a 3x3 router, and 64 times to form a 8x8 router.Toverifythefunctionalityof 8x8router,initiallya testbenchiswrittenandsimulated.Thesimulationresultsof the8x8routerareshowninFig 9.

Fig 9:Simulationresultsof8x8router

5.2 Power and Area Optimization

Before implementing it on the FPGA, we have written an algorithmtooptimizethepower.Thealgorithmisaimedto reduce the transitions in the message bits. For this we adopted the encoding and decoding techniques. Before transmittingthemessageisencodedusingthebitsb1and b2.Anycombinationofb1andb2canbetaken, butinthis project,wehavetakenb1as0andb2as1.Alltheevenbits areXORwithb1andoddbitsareXORwithb1andb2.The samedecodingtechniqueisusedatthereceivertoretrieve theoriginalmessage.AnexampleisshowninFig 10.From the figure we can see that the number of transitions is reducedfrom6to3,whichreducesthepowerconsumption duringtheprocessoftransmitting

Fig -11:PowerConsumptionReport

Table

2: Design Summary

Logic Utilization Used Available Utilization

No.ofSliceregisters 21,325 126,576 16% No.ofSliceLUTs 28,005 63,288 44% No.ofoccupiedSlices 9,974 15,822 63% No.ofIOBs 40 296 13%

ChipScope Tool is used to implement the project and additionalfilesrequiredtoimplementarewrittenandadded asasourcetothetopmodule.Dataportwidthistakenas57 and classified 16 ports for sending data, 16 ports for receivingdata,16bitsforthedata,4bitsforexpectedand arrivedportand1portforreset.Thentriggersetupisdone andwaveformisaddedtothewindow.Theimplementation anditsresultsareshowninFig 1.

Fig -10:PowerOptimizationTechnique

Aftersuccessfulverificationof8x8router,itisimplemented onFPGASpartan6.Thepowerconsumptionisobservedto be0.085WasshowninFig 11.Theareadetailsinthedesign summaryareshowninTable 2.

Fig -13:ImplementationresultsusingChipScope

6. CONCLUSION

ThevariouschallengesinSoCdesignmadetheresearchers lookforbetteralternativesthatmadeawayforNetworkon chiptechnology.TheNoCiscurrentlystillinitsinitialstages andemergingresearcharea.NoChasaremarkableimpacton the SoC design of next generation and multicore architectures. For this project, various surveys and recent

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research aspects of NoC, routing algorithms and network topology details were explored. An attempt was made to contributeintheresearchofNoCbyexploringthespaceof NoCrouterdesignwhichisapredominantcomponentofthe network. The main focus of this project is to design an efficient router since it is one of the most important components that determines various network parameters like latency, throughput and delay. The designing and simulationhavebeendoneusingthehardwaredescription languageVerilogHDLinXilinxISEtoolandimplementedon FieldProgrammableGateArray,usingChipScopeTool.

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BIOGRAPHIES

PreethiTS, AssistantProfessor,Dept.ofECE SapthagiriCollegeofEngineering Email: ts.preethi@gmail.com

JayanthKHolalkeri, Student,Dept.ofECE SapthagiriCollegeofEngineering Email: jayanth.holalkeri@gmail.com

ManasaDevGJ, Student,Dept.ofECE SapthagiriCollegeofEngineering Email: manasadev30@gmail.com

ManojMahadevBiradar, Student,Dept.ofECE SapthagiriCollegeofEngineering Email: mmbiradar1906@gmail.com

NageshRShanbhag, Student,Dept.ofECE SapthagiriCollegeofEngineering Email: nageshrshanbhag619@gmail.com