International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 09 Issue: 05 | May 2022
p-ISSN: 2395-0072
www.irjet.net
A Survey on Distributed Transactional Memory System with a Proposed Design for Parallel Processors Dr.G.Muneeswari1 1Professor,
School of Computer Science and Engineering, VIT-AP University, Amaravati, Andhra Pradesh, India ---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract - The main aim of this review is to investigate on a
comprehensive hardware support to transactional computing. In the modern technology many research work is going on with respect to the transactional requirement like hardware support, system software support and runtime environment support etc., For the concurrency control in transactions, many lock based synchronization methods have been evolved but they are limited to the speed of the execution. A method which can be proposed to an alternate to the lock based approach is transactional memory which allows the transaction to execute concurrently and later resolves the conflicts. This survey, reviews several variants of transactional memory schemes and two new design mechanisms are proposed for the implementation of transactional memory.
In this paper section 2 describes about literature survey and section 3 elaborates on the proposed TM design. Section 4 concludes the paper.
2. LITERATURE SURVEY This section presents some previous approaches to Transactional Memory as reported in the literature. The section also highlights the drawbacks of those in reference to the modern architectures. The actual representation of transactional memory was first introduced by Herlihy and Moss [1,4]. Their implementation was an extension to the cache-coherence protocol and cache mechanisms used in general-purpose architectures. The primary goal of this model was to provide a mechanism for implementing atomic operations with ease. However, this model imposes restrictions on the size of the transaction and cannot survive context switching.
Key Words: Transactional Memory, Cache Coherency, Concurrency, Context Switching, Locking, Hardware architecture
1. INTRODUCTION In the modern world, mostly speculation-based transaction processing and some programming language constructs and system software changes provides an alternate solution to the traditional concurrency control mechanisms. The objective of this proposal is to investigate on development of novel hardware architecture, related software techniques/algorithms and their respective implementations to support transactions on any concurrent environment as a whole, and as a fine grained technique applicable for many cores with course grain threaded, efficient distributed systems.
Transactional Lock Removal (TLR) [2,5]: With the help of this idea, the concurrency control mechanism using locks can be freely executed without enabling locks. This can be successfully completed irrespective of the existence of some module conflicts or changes in the code or non-existence of programmer. This model already incorporating all the relevant features of current computing systems and its associated features. The main advantage of this system is scalability, extended programming features and performance. Another major problem with the existing critical problem solution is blocking behavior and that is totally avoided in this transactional lock removal mechanism.
In a nutshell, for the multiple patallel architectures and for the multicore systems, inorder to provide concurrency support, locking techniques are basically used which leads to the complexity of the system software and overheads related to performance metrics. The main issues proposed for investigation are as follows:
Investigation on hardware architectures for deploying the Hardware Transactional Memory leads to provide a best solution for concurrency problems and a suitable alternate to locks.
To compare the proposed HTM system with lockbased systems from a performance and scalability points of view.
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The proposed HTM shall be enhanced to take into account issues like exception handling, paging and context switching.
Speculative Lock Elision (SLE) [3,6]: This method mainly focusses on multithreaded program execution. It is a hardware based approach where unwanted serializability using concurrent locks can be avoided in the execution phase. One of the vital part of the execution of threads here is that the read locks and write locks need not be obtained for the proper functionality of the code. Some of the instructions required for the concurrency control can be predicted and various threads can be executed parallel or concurrently in a critical section enforced by the similar locks. There is a chance for the misprediction and this may be identified using
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