International Research Journal of Engineering and Technology (IRJET) Volume: 09 Issue: 10 | Oct 2022
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e-ISSN: 2395-0056 p-ISSN: 2395-0072
A Comparative Analysis of Vedic multiplier with Array and Wallace Tree multiplier using Cadence Sheethal S Rokhade1, Dr. Kiran V2 1MTECH
1st year, Dept. of ECE, RV College of Engineering, Karnataka, India Associate Professor, Dept. of ECE, RV College of Engineering, Karnataka, India ---------------------------------------------------------------------***--------------------------------------------------------------------effectiveness of various computer problems is frequently Abstract - Among the main difficulties in VLSI design in 2
determined by the speed at which a multiplication operation may be done.
recent years has been power dissipation. In DSP blocks, multipliers are the primary causes of power loss. This project proposes effective architectures for 4-bit unsigned binary multipliers, including the Wallace Tree Multiplier, Vedic Multiplier, and Array Multiplier. The cadence 180nm technology was used for this implementation. In this design, multiplier circuits are effectively optimized in terms of area and power by first designing transistor level schematic circuits and then creating the test symbol. The implementation is made up of combinational parts such 1bit Full Adders, AND, XOR, Half Adders, and Inverter Circuits. The circuit analysis is done in terms of performance parameters like power consumption and transistor count. According to the analyses, the array multiplier's transistor count and power consumption were found to be 554, 7.457mw, the Wallace Tree multiplier, 500, 7.522mw, and the Vedic multiplier, 464, 7.443mw.
1.1 Array Multiplier An effective design for a combinational multiplier is an array multiplier. Using the "add and shift" technique, this multiplier multiplies using the conventional add and shift operation. Combinational circuits that form the product bit all at once can be used to multiple two binary values with a single micro-operation, making this a quick method of doing so since the only delay is the time it takes for the signals to travel through the gates that make up the multiplication array. Consider two binary values A and B with m and n bits each for the array multiplier. An array of m*n AND gates generates mn summands simultaneously. n(n-2) FA , n HA , and n2 AND gates are needed for the n X n multiplier. Additionally, the worst-case delay in an array multiplier would be (2n+1) td. The optimal number of components are used and more power is consumed by an array multiplier, but the delay is higher. Additionally, the area is increased due to the need for more gates, making the array multiplier less efficient. Consequently, despite the high hardware complexity, it is a quick multiplier.
Key Words: Multiplier, Power Dissipation, Array
Multiplier, Vedic multiplier, Urdhva Triyagbhyam, Wallace Tree Multiplier, Full Adder, Cadence Virtuoso Tool
1. INTRODUCTION The difficulty of power consumption in VLSI design is one of the most important. The power consumption of the circuit increases as chip complexity and transistor density do. Since it pulls more current from the power supply, higher power consumption increases chip temperature and has a direct impact on how long portable devices' batteries last. High temperatures compromise the functionality and dependability of circuits, necessitating increasingly sophisticated cooling and packaging techniques. In most digital signal processing (DSP) systems and most VLSI applications, multiplier is one of the fundamental hardware building components. A multiplier is frequently used in DSP applications such as spectrum analysis, digital filtering, and digital communications. Due to the fact that a large number of contemporary When designing DSP applications for compact, rechargeable batteries systems, power dissipation becomes a key consideration. Costly multiplications slow down the operation. The
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Fig 1: Block Diagram of 4 x4 Array Multiplier
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