International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 11 Issue: 08 | Aug 2024
p-ISSN: 2395-0072
www.irjet.net
Performance Characterization Of n-Channel Hetero-Dielectric Gate Tunnel Field effect Transistor (TFET) In Sub-Micron Region Tan Chun Fui1, Ajay Kumar Singh2 1 Senior Lecturer, Faculty of Information Science Technology, Multimedia University-Jalan Ayer Keroh Lama,
Melaka, Malaysia.
2 Professor, Electronics and Communication Engineering NIIT University, Alwar, Rajasthan India.
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Abstract - To fulfill the performance demands of low-power
performance, but in the post-scaling era, short channel effects (SCEs) and increased leakage current have undermined its efficacy [2-3]. Various non-planar structures, including multi-gate devices and alternatives to conventional CMOS technology, have been proposed in literature [4-9]. Suppression of leakage current without compromising ON current is a primary challenge in the nanoscale era, where leakage current significantly impacts device stability. Nanowire transistors, particularly tunnel field-effect transistors (TFETs), have been suggested to manage leakage current [7,10,15].
mobile devices, a high ION/IOFF ratio at low-VDD necessitates a specific device design. TFETs are increasingly favored due to their superior characteristics like low subthreshold slope and high transconductance compared to MOSFETs. However, silicon-based TFETs exhibit a drawback of low on-state current, limiting their applicability in high-performance scenarios. To address this issue, employing a narrower band gap material such as Ge can enhance tunneling efficiency at the source side. Furthermore, mitigating the larger ambipolar current associated with Si-TFETs can be achieved through a nchannel hetero-gate-dielectric (HGD) TFET. This research aims to propose and characterize a novel TFET structure leveraging hetero structure and hetero-gate-dielectric advantages, thereby enhancing ION while suppressing ambipolar current. The structure incorporates a heterodielectric Buried Oxide (BOX) on the doped substrate to reduce ambipolar current. The source-to-gate overlap technique is employed to attain the desired subthreshold slope (SS). All simulations are conducted using a 2-D TCAD simulator, specifically Atlas Silvaco. The structure is optimized based on metrics such as ION/IOFF ratio, and simulation results are compared with existing structures in literature for performance evaluation.
TFETs are poised to replace planar MOSFETs in the future [13,16,17]. Despite TFETs exhibiting a reduced subthreshold slope (SS) at room temperature (60 mV/decade), they suffer from two main drawbacks: lower ON current and higher ambipolar current [14-18]. TFETs with gate-drain overlap structure have been proposed to reduce ambipolar current [9], albeit at the expense of reduced chip density. The ON current of TFET devices can be enhanced by employing highk dielectric materials as gate insulators [18], albeit with increased ambipolar current. In addressing these drawbacks, hetero-dielectric gate (HDG) TFETs have been proposed in literature. HDG TFETs utilize SiO2 at the drain to decrease ambipolar current and a high-k material partially near the source to boost ON current.
Key Words: TFET, Heterro Gate Dielectric, Ambipolar current, ON current, simulation.
In this paper, we have studied the electrical behaviour of the n-channel HGD TFET devices in terms of surface potential, tunneling width, drain current and ambipolar current. We have ignored the source/drain depletion width due to heavy doping and quantum confinement effect due to silicon film thickness (> 3 nm). The structure of this paper is given as follows: Section 2 describes device structure of the model. Section 3 discusses the electrical behaviour of the proposed structure and at the end, we conclude the paper in section 4.
1.INTRODUCTION Previously, MOSFET miniaturization was effective for circuit performance enhancement, but in the post-scaling era, its effectiveness is hindered by increased leakage current and short channel effects (SCEs) [1-3]. To address these challenges, researchers have proposed various alternative structures beyond planar ones [4-6], including multi-gate devices and those employing different materials to replace standard CMOS technology [7-9]. Leakage current emerges as a significant issue in the nanoscale regime, disrupting device stability. Thus, controlling leakage current without compromising ON current becomes a critical challenge. Nanowire transistors, particularly tunnel field-effect transistors (TFETs), have been suggested as potential replacements for planar MOSFETs [10-14]. Formerly, downsizing MOSFETs effectively boosted circuit
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2. DEVICE STRUCTURE 2.1 Structure of n-channel HGD TFET The 2-D structure and coordinate system of the proposed n-channel hetero-gate-dielectric TFET (HGD TFET) is shown in Figure 1 below.
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