International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 11 Issue: 06 | Jun 2024
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p-ISSN: 2395-0072
Application of Vertical Transistors in Advanced Memory and Logic Development Selva Lakshman Murali, Arizona State University ------------------------------------------------------------------------***----------------------------------------------------------------------
very high chance that the adjacent transistors interfere each other. To prevent them from interfering, we place dummy gates between the transistors which occupies additional area on the chip. VTFET’s does not need these dummy gates between them – they instead use something called as shallow trench isolation which doesn’t require any additional space on the chip. The current in VTFET’s also changes it direction from the traditional FinFET’s, which is perpendicular to the surface of the chip. This gives us the flexibility to change the length of the gate to control the current. to as "16/14," but real "7nm" node circuit densities will necessitate the next generation of lithography, EUV at 13.5nm wavelength. The cost of the chip, which is challenged by the requirement for unique cost-intensive patterning techniques, is the key to acceptance in the electronics device area. Given the higher wiring parasitic, the ability to gain more performance at constant chip power will be the key to adoption in the server area. To get to mature 7nm nodes, new materials will be required in all scenarios.[3]
Abstract—Vertical Tunnel Field Effect Transistors (VTFET) has a different working principle than traditional FET’s and are said to be more beneficial than the traditional FinFETs that we have been using for decades. This paper presents a new device architecture, which can be shared by a wide range of sorts of semiconductor transistors. Here, the significance and prerequisites of the vertical transistor in the VLSI industry alongside its device processing have been illustrated. It moreover talked about the benefits and applications in memory, logic technology alongside analog development over past years. Vertical semiconductors have helped decrease expenses per bit for flash memory and it has assisted with diminishing the leakage current in most recent innovation hubs. Looking for better performing devices specialists are presently investigating 3D designs, for example, vertical semiconductors, whose benefits incorporate low power consumption, smaller current leakage towards the bulk, and better suitability for adaptable hardware. Keywords: Vertical Tunnel Field Effect Transistor (VTFET), atomic layer affidavit (ALD), Silicon-On-Insulator (Sal), gate-all-around (GAA), 3D designs, Memory application.
I. INTRODUCTION Modern electronics are mostly flat, with millions of planar silicon transistors lying on a chip’s surface. These are getting faster and efficient every day because of the tiny chips that power these electronics evolving at an unprecedented rate. Our understanding at transistors or chips starts with a term called Moore’s Law. This law states that the number of transistors on a chip double about every two years. The speed of the chip depends on the number of transistors on the chip. As the number of transistors keep on increasing year by year, we should now be worried about running out of space on the chip. One solution to overcome this problem is, to find a new technology where space is not the constraint, VerticalTransport Field Effect Transistors. This is a new technology to overcome the problem with the traditional MOSFET’s. In VerticalTransport Field Effect Transistors (VTFET), the transistors are arranged perpendicular to the plane of the chip. This eliminates the space constraint and allows the engineers to pack a lot more transistors vertically in a given space. The VTFET’s are said to dominate the speeds of traditional FinFET’s. The transistors that we currently use has three terminals on the same plane: gate, source & drain. When a small voltage is applied to the gate terminal, the transistor will turn on and the current flows from source to drain. When these transistors are placed on the chip, there is a
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Fig. 1. FET Configuration
Fig. 2. VTFET Configuration
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