International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 11 Issue: 05 | May 2024
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p-ISSN: 2395-0072
DESIGN OF 16 BIT RISC PROCESSOR FOR ARITHMETIC AND LOGICAL OPERATIONS IN XILINX VIVADO K.G.Venkata Krishna1, N.K.KamalaDevi2, K.Vishnu Varma3, A.Yedukondalu4 1 Assistant Professor, Department of Electronics and Communication Engineering, Krishna University College of
Engineering and Technology Krishna University, Machilipatnam Andhra Pradesh, India.
2UG Student, Dept. of ECE, Krishna University College of Eng. &Tech, Machilipatnam, A.P, India.
3UG Student, Dept. of ECE, Krishna University College of Eng. &Tech, Machilipatnam, A.P, India. 4UG Student, Dept. of ECE, Krishna University College of Eng. &Tech, Machilipatnam, A.P, India.
---------------------------------------------------------------------***--------------------------------------------------------------------2. LITERATURE REVIEW
Abstract - The Re prefers a more condensed,
straightforward set of instructions that all execute in the same amount of time. This processor preserves functional units without compromising performance. The design makes advantage of an architecture known as Harvardd, which includes separate data and instruction memory. A word of instructions has 24 bits in total. The CPU supports three addressing modes in addition to sixteen instructions. It contains sixteen general-purpose registers. Any register has the capacity to store 16 bits of data. The procedure performs 11 arithmetic and logical operations. Every module is developed and tested separately at every stage of implementation before being properly mapped into the toplevel module. The simulation results are verified using Xilinx Vivado 2023.1 once the design input and synthesis are finished using the same tool.
2.1 S. Lad and V. S. Bendre, "Design and Comparison of Multiplier using Vedic Sutras," 2019 5th International Conference On Computing, Communication, Control And Automation (ICCUBEA), Pune, India, 2019, pp. 1-5 Fast processing units are necessary for many real-time applications in modern computerized era. The basic building elements of these units are ALU and MAC, which are necessary for quick and effective execution. Digital signal processors primarily use multipliers as their primary component. ALU and MAC performance can be improved by modifying registers, multiplier, and adder to retain correctness and speed up execution. Due to the growing delays restrictions, the design of quicker multipliers is prioritized for implementation in processors. It is crucial to create quicker multipliers in order to increase multiplication speed.
Key Words: RISC, 16-bit, VLSI, verilog
1.INTRODUCTION When the performance of CISC fell short of expectations and the controller design grew more challenging, people started to consider alternate approaches. It has been found that when a CPU interfaces with memory, speed is lost. Reducing the complexity of the instruction set was the only option to raise CPI. Simpler in terms of design than in terms of functioning. As a result, the CPU is not required to access memory for very many instructions in a typical RISC architecture—probably only load and store. Ultimately, pipelining increased performance. Only a few additional registers can provide a new level of performance by lowering CPU and increasing throughput. Consequently, the instruction may be successfully executed in one clock cycle. It's a common misperception that when the term "Reduced Instruction Set Computer" is used, instructions are only removed to create a smaller set of instructions. In fact, RISC instruction sets have grown in size over time, and several of them now include more instructions than many CISC CPUs.
2.2 Balpande Vishwas V, Abhishek B. Pande, Meeta J. Walke, Bhavna D. Choudhari and Kiran R. Bagade. “Design and Implementation of 16 Bit Processor on FPGA.” (2015). This project involves the design of a 16-bit RISC processor and the Verilog HDL modeling of its constituent parts. Harvard architecture is the basis of the processor. This instruction set's extreme simplicity provides an indication of the sort of hardware that should be able to correctly execute the set of instructions. More sophisticated blocks like an ALU and memory have been built and simulated in addition to the sequential and combinational processor building blocks like adders and registers. In this project, comprehensive structural ALU modeling, beginning with half adders, has been completed. Ultimately, the semicustom layout was created just for ALU. 2.3 Seung Pyo Jung, Jingzhe Xu, Donghoon Lee, Ju
Sung Park, Kang-joo Kim and Koon- shik Cho, "Design & verification of 16 bit RISC processor," © 2024, IRJET
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