International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 11 Issue: 04 | Apr 2024
p-ISSN: 2395-0072
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DESIGN AND VERIFICATION OF 32-BIT VEDIC MULTIPLIER K.G.VENKATA KRISHNA1, A.SUPRIYA2, R.AKHIL3, CH.PAVAN KUMAR4, D.KARIMULLA5 1Assistant Professor, Dept of ECE, Krishna University College of Engg & Tech,
Machilipatnam, Krishna-521004, AP, India
2,3,4,5 UG Students,Dept of ECE, Krishna University College of Engg & Tech,
Machilipatnam, Krishna-521004, AP, India ---------------------------------------------------------------------***--------------------------------------------------------------------application-specific integrated circuit (ASIC) used in data Abstract - The Vedic sutras of classical Vedic mathematics, the proposed research project describes the modified binary Vedic multiplier. It offers adjustments to the Vedic multiplier that has been prototyped. There has been an improvement in both device use and time delay with the updated binary Vedic multiplier, which is preferred. In Verilog HDL, the suggested method was created and put into practice. The Xilinx Vivado tool is used for HDL simulation and synthesis. Simulation results are also displayed. The simulation was performed for a 32bit multiplication operation. Greater sizes can be used with this adjusted multiplication method. Comparisons are made between the results of this multiplication method and current Vedic multiplier methods.
processing. When die area, power dissipation, and especially operating speed are of concern, it is frequently the most important circuit component. Arithmetic units like multipliers, adders, and comparators form the foundation of both data-path and addressing units. Lastly, the binary addition is the fundamental operation included in the majority of mathematical components. In addition to doing basic operations like incrementing and magnitude comparison based on binary addition, adders may also perform simpler operations like adding two integers. Thus, the most significant arithmetic operation is binary addition.
Key Words: Vedic-multiplier, Ripple carry adder, Carry save adder, VerilogHDL
2.1 S. Lad and V. S. Bendre, "Design and Comparison of Multiplier using Vedic Sutras," 2019 5th International Conference On Computing, Communication, Control And Automation (ICCUBEA), Pune, India, 2019, pp. 1-5
2. Literature Review
1.INTRODUCTION
Fast processing units are necessary for many realtime applications in modern computerized era. The basic building elements of these units are ALU and MAC, which are necessary for quick and effective execution. Digital signal processors use multipliers as its primary component.To keep things accurate. To boost the rate of execution, registers, multipliers, and adders must be changed in order to improve the performance of the ALU and MAC. The growing limits on delay call for the design of quicker multipliers to be implemented in CPUs. It is crucial to create quicker multipliers in order to increase multiplication speed.
Research scholar Bharati Krishna provided a more succinct explanation of Vedic mathematics, stating that it is comprised of 64 sutras and 13 sub-sutras. This makes solving mathematical equations for computations easier.Prehistoric Vedic Mathematics was made more advanced by Swami Bharati Krishna Tirthaji Maharaj, a Shankaracharya from Goverdhan Peath. It makes sense and is both straightforward and consistent. As a result of Vedic mathematics becoming more and more common, both in India and the rest of the globe, it is a highly popular study topic. Digital signal processing must carry out tasks such as frequency transformations (DFT, FFT, and DCT) and frequency domain filtering (FIR, IIR). Multiplications are an essential hardware component for these tasks. For this reason, choosing how to display the entire structure depends in large part on how the multiplier is presented. This is due to the fact that the multiplier is the framework's slowest and most laborious element. Therefore, a notable test for the framework architects is the improvement of the multiplier speed and area. The application of ancient Vedic mathematical methods can successfully overwhelm this exam.
2.2 Balpande VishwasV, Abhishek B.Pande, Meeta J.Walke, Bhavna D.Choudhari and Kiran R. Bagade. “Design and Implementation of 64 Bit Processor on FPGA.” (2015). This assignment involves utilizing Verilog HDL to model the components of a 64-bit RISC CPU and create it. The Harvard architecture serves as the basis for the CPU. The very basic instruction set used here provides insight into the sort of hardware that should be able to correctly execute the set of instructions. Beyond the basic sequential and combinational processor building blocks, such registers and adders, more intricate blocks, like ALUs and memory, have been built and modeled. In this research, the
1.1 Need of Multiplier Architecture The data route is the central component of any microprocessor, digital signal processor (DSP), and
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