International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 11 Issue: 04 | Apr 2024
p-ISSN: 2395-0072
www.irjet.net
DESIGN AND SIMULATION OF DATA SEGMENTATION SECTION CODE FOR SPACE COMMUNICATION K.G.VENKATA KRISHNA1, B.LAVANYA2, K.SRAVANI3, K.JAGADEESH4 1 Assistant Professor , Dept of ECE , Krishna University College of Engg & Tech,
Machilipatnam , Krishna-521004 , AP , India
2,3,4 UG Students , Dept of ECE, Krishna University College of Engg & Tech,
Machilipatnam , Krishna-521004 , AP , India ---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract - In the interest of technological scalability, bit
continue operating as intended even when one or more of its component parts fail is known as fault tolerance. A method called "hamming code" uses a set of ECC to identify and fix bit mistakes in data transmission and storage.
mistakes caused by single occurrences or repeated cell disruptions by environmental elements like cosmic radiation, alpha and neutron particles, or the highest temperature in space can cause on-chip memory in a die to corrupt data. Through a communication channel, error detection and correction algorithms (ECC) identify and fix faulty data. This work proposes an enhanced divide-symbol based error correcting 2-dimensional code to decrease radiation-induced MCUs in memory for space applications. The XOR technique was used to examine the diagonal, parity, and check bits used in the data encoding process. Once more, an XOR operation was carried out between the encoded bits and the recalculated encoded bits in order to retrieve the data. Following analysis, there is a procedure of verification, selection, and correction. Xilinx Vivado, which was built in Verilog HDL, was used to simulate and synthesize the suggested methodology. In contrast to established techniques, this encoding and decoding procedure uses less energy, takes up less space, and requires less time.
2. LITERATURE SURVEY 2.1 R. C. Baumann (2005), “Soft errors in advanced computer systems,” IEEE Des. Test. Comput., vol. 22, no. 3, pp. 258-266. Due to the reduction in device feature size and supply voltage, achieving soft error reliability in sub-micrometer digital circuits is becoming extremely challenging. We consider the problem of choosing the gate sizes in a combinational logic circuit in order to minimize the soft error rate (SER) of the circuit. This problem can be solved using the heuristic as well as the greedy-based approaches for small-size problems; however, when the circuit size increases, the computational time grows exponentially, and hence, the previous methods become impractical. This paper proposes a novel technique for soft error tolerant design of large-scale combinational circuits using a coneoriented gate sizing. Circuit partitioning is used to split the circuit into a set of small sub-circuits. The gates of subcircuits are resized, such that the entire circuit SER is reduced based on a new soft error descriptor metric. The proposed cone-oriented gate sizing framework is used for selective gate sizing, leading up to 31% SER reduction with less than 17% area overhead when applied to large-scale benchmarks. The results also show that the proposed method is 21% more efficient and up to 292 times faster when compared with that obtained using a similar work based on the sensitive-based gate sizing scheme
Key Words: —Error Correction Code, Multiple Cell Upsets, Encoder, Parity, Decoder, Memory
1.INTRODUCTION An earlier error detection approach required a parity. Each character was processed by appending an additional bit. Many factors, including the type of parity and the amount of logic-one bits in the data character, make the bit stubborn. Alliteration code is an additional code structure that provides error detection information. The code doodle displays a bit across channel to achieve error-free communication. Data are separated into data bits and data blocks in a data stream. Each block is sent out for the predetermined amount of times. It is ineffective as parity since the same mistakes cause greater issues. They are straightforward and utilized in the number station transmission process. The process of identifying mistakes and transforming the original data into error-free data is known as error correction. The ability of a system to
© 2024, IRJET
|
Impact Factor value: 8.226
2.2 C. L. Chen and M. Y. Hsiao (1984), “Errorcorrecting codes for semiconductor memory applications: A state-of-the-art review,” IBM J. Res. Develop., vol.28, no. 2, pp. 124-134. This paper presents a state-of-the-art review of errorcorrecting codes for computer semiconductor memory applications. The construction of four classes of errorcorrecting codes appropriate for semiconductor memory
|
ISO 9001:2008 Certified Journal
|
Page 2366