International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 11 Issue: 11 | Nov 2024
p-ISSN: 2395-0072
www.irjet.net
PERFORMANCE OPTIMIZATION OF 32-BIT ALU IMPLEMENTED WITH REVERSIBLE LOGIC USING PIPELINING AND CLOCK GATING ON FPGA Chaithra K1, Dr. K N Rajanikanth2 1Post Graduate Student, Dept. of ECE, BMS College of Engineering, Bengaluru, India 2Associate Professor, Dept. of ECE, BMS College of Engineering, Bengaluru, India
---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract - Modern electronic devices face challenges in
preserving information, enabling energy recovery that is typically wasted. The Vedic multiplier method, rooted in ancient Indian mathematics, enhances multiplication efficiency and simplifies calculations.
managing power dissipation, making efficient design crucial. This paper presents a high-performance ALU that uses reversible logic gates and Vedic multipliers, implemented with Xilinx Vivado. Reversible logic gates help reduce power consumption and heat by allowing bidirectional data processing, while Vedic multipliers improve arithmetic speed using traditional techniques. The ALU also features clock gating for energy savings and input-based pipelining to boost processing efficiency. ALU is capable of handling various operations, this design offers better power efficiency and speed than conventional ALUs, making it ideal for mobile and embedded applications. Key Words: ALU (Arithmetic and logical unit), FPGA (Field programmable gate array), Reversible logic gates, Urdhva Tiryagbhyam, Vedic multiplier.
Lately, engineers have been exploring novel methods to develop quicker and more energy-efficient ALUs utilizing reversible gates and Vedic multipliers techniques. These sophisticated techniques have considerable promise for enhancing both the efficiency and performance of ALU designs. Utilizing reversible gates that reduce energy waste and Vedic multipliers that streamline intricate calculations, these methods provide significant benefits for contemporary computing systems. This paper will extensively examine the design process utilizing these methods, along with simulated outcomes to confirm their efficacy and showcase their improved performance.
1. INTRODUCTION
2. CONCEPT
In the rapidly evolving technology of today, numerous devices are created with incredibly tiny sizes, often measured in nanometers, and the Arithmetic and Logic Unit (ALU) is essential in these systems. The ALU is in charge of carrying out mathematical and logical tasks on binary data, made up of zeroes and ones, the basic computer language. Functioning as the primary component of the central processing unit (CPU) to handle calculations, the arithmetic logic unit (ALU) decodes CPU commands and performs operations like addition, subtraction, multiplication, and comparisons to facilitate effective data processing. After getting binary inputs, the ALU performs tasks such as adding numbers and then transmits the outcomes to the CPU for additional purposes. The ALU also carries out logical operations such as AND, OR, XOR, and NOT, in addition to arithmetic functions, which are essential for data comparison and decision-making. The ALU, as a key element in computer design, plays a crucial role in performing a wide range of functions, from basic math operations to complex data handling, and is vital in today's computer systems.
Reversible gates are essential in modern circuit design since they allow computations to move in both directions while maintaining all information. This makes them a unique and efficient tool for managing information. Unlike traditional logic gates that can lead to information loss, reversible gates allow for the retrieval of the original input from the output, making them highly beneficial in various applications. In reversible computing, preserving information is a core concept. Each combination of inputs in a reversible gate must correspond uniquely and reversibly to the output, ensuring that no information is lost during processing. This trait distinguishes reversible gates from irreversible ones, offering the possibility of reduced power use and improved efficiency. In some cases, extra inputs or outputs are needed to guarantee that a circuit can be reversed. The total number of inputs, including fixed inputs, must equal the overall number of outputs, even if certain outputs, known as "garbage" outputs, are not essential for the function. These "garbage" results are crucial for preserving a one-to-one link between inputs and outputs. Figure 1 depicts a reversible logic gate of size n*n with n inputs and n outputs, where every input (In) is connected to its matching output (On).
When designing an ALU, it’s crucial to prioritize speed and energy efficiency, making sure it operates quickly while consuming minimal power. Certain methods, such as employing reversible gates and Vedic multiplication techniques, can assist in attaining these objectives. Reversible gates are unique as they can handle data while
© 2024, IRJET
|
Impact Factor value: 8.315
|
ISO 9001:2008 Certified Journal
|
Page 612