International Research Journal of Engineering and Technology (IRJET) Volume: 11 Issue: 10 | Oct 2024
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e-ISSN: 2395-0056 p-ISSN: 2395-0072
Artificial Intelligence in VLSI Physical Design of Circuits to Optimize Power, Performance and Area (PPA) 1Selva Lakshman Murali, 1MSE, Arizona State University, AZ-USA
---------------------------------------------------------------------------***--------------------------------------------------------------------------Abstract– The increasing complexity of Very LargeII. Overview of VLSI Physical Design Scale Integration (VLSI) circuits presents significant challenges in achieving Power, Performance, and Area (PPA) goals. Traditional approaches to physical design often involve manual or heuristic-driven processes, which are time-consuming and may not fully exploit optimization opportunities. This paper explores the application of Artificial Intelligence (AI) in automating and improving various stages of the VLSI physical design process. By leveraging machine learning (ML) algorithms, AI can assist in achieving optimized PPA goals, accelerating the design cycle, and enhancing chip performance. Key stages, including floorplanning, placement, routing, standard cell design, and power grid optimization, are examined in the context of AI-driven techniques.][15][16][14]Case studies demonstrating how AI can reduce design iterations, enhance performance, and minimize power consumption are presented. Index Terms-- VLSI, Physical Design, Artificial Intelligence, Machine Learning, Power, Performance, Area, PPA, Optimization. I.
INTRODUCTION
The increasing complexity of Very Large-Scale Integration (VLSI) circuits presents significant challenges in achieving Power, Performance, and Area (PPA) goals. Traditional approaches to physical design often involve manual or heuristic-driven processes, which are time-consuming and may not fully exploit optimization opportunities. This paper explores the application of Artificial Intelligence (AI) in automating and improving various stages of the VLSI physical design process. By leveraging machine learning (ML) algorithms, such as supervised learning, unsupervised learning, and reinforcement learning (RL), AI can assist in achieving optimized PPA goals, accelerating the design cycle, and enhancing chip performance. Key stages, including floorplanning, placement, routing, standard cell design, and power grid optimization, are examined in the context of AIdriven techniques. Case studies demonstrating how AI can reduce design iterations, enhance performance, and minimize power consumption are presented.
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The physical design process consists of multiple stages, each focusing on transforming a high-level circuit description into a geometric layout. The key stages of the physical design process are outlined below: ●
Partitioning: Dividing the circuit into smaller blocks to make the design process more manageable.
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Floorplanning: Determining the relative positions of the blocks and the allocation of routing resources.
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Placement: Deciding the exact positions of individual cells within the blocks, while considering timing, area, and power constraints.
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Routing: Establishing the physical connections between placed cells while minimizing wirelength and ensuring signal integrity.
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Clock Tree Synthesis (CTS): Building a balanced tree to distribute the clock signal uniformly across the chip.
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Timing Closure: Ensuring that all timing constraints are satisfied after placement and routing.
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Design Rule Checking (DRC): Verifying that the design adheres to manufacturing rules.
Each stage of the design introduces optimization challenges that can be enhanced through AI/ML techniques.
III. Machine Learning Applications in Physical Design Machine learning models have been developed to assist in optimizing various stages of the VLSI physical design process. The key ML techniques include supervised learning, unsupervised learning, reinforcement learning, and deep learning. Below is an exploration of their application in different stages of physical design.[1]
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