International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 10 Issue: 07 | July 2023
p-ISSN: 2395-0072
www.irjet.net
Experimental Electrical Characterization Results of PLL Jitter Nidhi1, M. Ejaz Aslam Lodhi2, Mohd. Safdar Imam3 1M. Tech. Scholar, Department of ECE, Indira Gandhi Delhi Technical University for Women, Delhi, India
2Senior Assistant Professor, Department of ECE, Indira Gandhi Delhi Technical University for Women, Delhi, India 3Sr. Manager, ST Microelectronics Pvt Ltd, Greater Noida, India
---------------------------------------------------------------------***--------------------------------------------------------------------2. PLL AND ITS BASIC BUILDING BLOCK Abstract - In this letter, we aim to validate and check the electrical characteristic of Analog IPs embedded in SoCs. Analog blocks are more prone to the external behavior because the human world can talk and think in an analog manner. Hence, not easy to satisfy the requirement from an analog point of view compared to digital circuits which can be simulated and tested. Furthermore, when an analog comes into the picture, the noise insertion and its interface connections start creating problems in satisfying the actual specifications. Electrical characteristics validated on SoCs are single period and long-term Jitter for PLLs and their functionality according to the specifications. Further, our work will be based on improving the test bench with automated test environment, since automation helps to reduce human errors and make the testing process more reliable.
A PLL consists of three key components:
1. Phase detector (a phase comparator or mixer). It
compares the phases of two signals and generates a voltage according to the phase difference. It multiplies the reference input and the voltagecontrolled oscillator output.
2. Voltage-controlled
oscillator produces a sinusoidal signal whose frequency matches closely the low-pass filter's centre frequency.
3. Low-pass filter: the loop filter plays a crucial role
in smoothing and shaping the control voltage that is applied to the Voltage-Controlled Oscillator (VCO). Its primary function is to attenuate the highfrequency alternating current (AC) components of the phase detector's output signal while allowing the low-frequency components (DC) to pass through relatively unattenuated. This action smoothens and flattens the signal, making it more DC-like or continuous.
Key Words: PLL, Jitter, Noise, Analog, SoC, Validation.
1. INTRODUCTION A phase-locked loop (PLL) is an electronic circuit that continuously modifies its voltage or voltage-driven oscillator's frequency to match that of an input signal. PLLs can produce, maintain, modulate, demodulate, filter, or recover a signal from a communications channel[1] that is "noisy" because data is being interrupted. PLLs (PhaseLocked Loops) are essential components in many wireless and radio frequency (RF) applications due to their ability to generate stable and precise frequencies. They play a crucial role in various communication systems and devices, including Wi-Fi routers, broadcast radios, walkie-talkie radios, televisions, and mobile phones. Here's a brief explanation of how PLLs are used in these applications, which further helps in low power and delay electronics device[8]. A PLL is used for clock generation inside SoC, and its working and application are pretty similar to a frequency synthesizer in a cellphone to match the cellphone frequency with desired frequency of reception of the message signal, then communication can take place. The core function of a PLL is to synchronize the phase and frequency of an output signal with that of a reference signal. This closed-loop feedback system allows the PLL to lock onto and track the phase and frequency of the reference signal, making it an essential tool in many applications. It is a system of analog and digital components connected in a "negative feedback" topology rather than a single component.
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To better understand the operation, let`s start with the basic building blocks of PLL
Figure 1: Basic Block Diagram of PLL The phase detector (PD) compares the phase difference between the input signal's frequency (f_ref) and the feedback signal's frequency (f_out). It does not generate a DC voltage directly proportional to the phase difference, but rather it produces a voltage that represents the instantaneous phase error between these two signals. The phase detector can be represented by a phase comparator or a multiplier. When using a multiplier as the
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