International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 10 Issue: 07 | Jul 2023
p-ISSN: 2395-0072
www.irjet.net
Design And Analysis Of 64-Bit Adders In Cadence Using Different Logic Families 1Gadamsetty Vyshnavi, 2Pasupulati Vijay Krishna 1Student, Dept. of Electronics and Communication Engineering, GITAM University, Telangana, India 2Student, Dept. of Electronics and Communication Engineering, GITAM University, Telangana, India
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Abstract -In this project, we focus on the design and
In mobile applications, designers must work within very tight leakage performance specifications to meet battery life and package cost goals for their products. A designer's concern about the level of leakage current has nothing to do with ensuring correct circuit operation but with minimising power consumption.
analysis of 64-Bit Adders using different logic families: CMOS, Pseudo-NMOS, and Transmission Gate. Full-Adder circuits are digital logic circuits capable of adding two input bits and a carry-in bit and generating a sum and carry-out bit as outputs. They are an essential building block for larger Adders and are widely used in digital circuits. To design the Adder circuits, we use the design tools provided by Cadence. We implement the Full-Adder circuits using the appropriate MOSFETs for each logic family and cascade several Full-Adders together to form the larger 64-Bit Adder. Once we design the adder circuits, we use simulation tools to verify their functionality and compare their power and performance characteristics. We measure the power consumption of the adder circuits under different operating conditions and analyze the speed of the adder circuits to determine which logic family offers the best trade-off regarding power efficiency and performance. Based on the results obtained from different logic families, we can identify the logic family that provides the best combination of speed and power consumption.
In this project, all the designs are based on the structure of the Ripple Carry Adder. Since it is a 64-Bit Full-Adder, we cascaded 1-Bit, 4-Bit, 8-Bit, 16-Bit, and 32-Bit together to form a 64-Bit using Ripple carry Adder for each logic family. These Full-Adders of all logic families and their respective symbols are designed in GPDK090 and analyzed using the Cadence Virtuoso platform.
1.1 Full Adder A Full-Adder is a digital circuit. A 1-Bit Full-Adder adds three 1-Bit inputs named X, Y, and Cin. X and Y are the operands, and Cin has some carryover from the previous less critical stage. A Full-Adder is typically one component of a cascaded adder that adds binary numbers of 4, 8, 16, 32, etc. bits. This circuit produces a 2-Bit output Carry (Cout) and Sum (S).
Key Words: Full Adder, Ripple Carry Adder, CMOS, Pseudo-NMOS, Transmission Gate, Power Analysis
Equations: These equations are obtained from the truth table of 1-Bit Full-Adder using K-maps for S and Cout. Fig 1 shows the circuit diagram designed from these equations:
1. INTRODUCTION We are seeing rapid growth in the field of integrated circuit (IC) technology. All ICs must be designed in an optimized manner to meet all requirements of speed, space-saving, and low power consumption. One of the circuits that most ICs occupy is the ALU, which is a combination of arithmetic and logic units. The two most important arithmetic units are adders and multipliers.
Sum(S) = (X XOR Y) XOR Cin Carry(Cout) = X·Y + Y·Cin + X·Cin
Adders are the heart of arithmetic circuits, and many complex arithmetic circuits are based on addition. Due to the widespread use of this operation in arithmetic functions, adders in mobile applications are of interest. Several variations of different logic styles have been proposed in recent years to implement 1-Bit adder cells. These summing cells are typically intended to reduce power consumption and increase speed. These studies also explore different approaches to implementing adders using CMOS technology. Fig -1: Circuit Diagram of Full-Adder
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