International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 10 Issue: 06 | Jun 2023
p-ISSN: 2395-0072
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Study and Analysis of Low Power SRAM Memory Array at nano-scaled Technology Sonali Verma1, Dileep Kumar 2 Department of Electronics & Communication Engineering, Goel Institute of Technology and Management, Faizabad Road near Indira Canal Lucknow 2 Department of Electronics & Communication Engineering, Goel Institute of Technology and Management, Faizabad Road near Indira Canal Lucknow 1
---------------------------------------------------------------------***--------------------------------------------------------------------et al. [4] a PMOS substrate offset on a 12T cell proposed as a Abstract - The cache memory design of microprocessors
means of producing the same effect. On the other hand, such techniques need more room to implement the PMOS body bias or a reference voltage-generating array. In addition, columns are used to store the operands for the aforementioned operations [2][5][6][7], It is not how data is stored in standard SRAM (static random-access memory), and hence necessitates extra data movement. DRAM cells can operate without a steady stream of electricity. However, DRAM relies on periodic pre-charging of its storage capacitors. Choi et al. DRAM array cells as well as a sense amplifier (SA) worked together to complete the logic tasks [8]. Ali et al. a DRAM array that can-do vector addition [9]. Yu et al. made ternary multiplication possible with a 4T2C DRAM chip [10]. Yet, the read operation on many rows might lead to data corruption whenever IMC (in-memory computing) is implemented in DRAM. Therefore, this disadvantage necessitates the insertion of extra safety circuits.
makes use of Static Random-Access Memory (SRAM) cells. Their efficiency is crucial because they are an integral part of the central computer system. Only 10–15 percent of a modern system on a chip's (SoC) transistors are dedicated to logic, whereas the rest are used for cache memory, increasing the performance strain. On top of that, the AI-reliant nature of today's implantable, portable, as well as wearable electronic equipment highlights the need for a robust SRAM architecture for CIM. Modern mobile communication devices include ample storage space for users' extensive media collections. Here, we adapt the Multi-threshold CMOS design to create a low-power SRAM cell. Power usage and read/write cycle Access Time can be lowered by using CMOS transistors with various threshold voltages. This work proposes a novel approach to reducing leakage in the idle state to cut down on power usage. The power usage of an SRAM cell is affected by the temperature, size of the transistors as well as the voltage used in the test. Data storage is an important function of several electronic components, specifically digital ones. The overall power usage of an SRAM is heavily influenced by leakage current. The research utilized a 1-bit 6T SRAM cell to construct a 1 KB memory array using CMOS technology and 0.6 volts for the supply voltage. In this section, we use deep submicron (130nm, 90nm, and 65nm) CMOS technology and the six-transistor (6T) SRAM cell to analyze how varying topologies impact the performance of a 12T SRAM array.
2. LITERATURE REVIEW Sudhakar Alluri et.al [11] In this study, we construct and simulate six-transistor FINFET-based static RAM cells then analyze the challenges inherent in their design as well as the metrics by which their success is measured. Minimizing SCEs, drastically reducing the maximum allowed duration, measuring the tremendous reliability of this process in a weak-power region, and so on. Power dissipation, leakage current, sub-threshold current, and static noise margin for FINFET and MOSFET 6 transistor static RAM were evaluated at the 45nm node. While modern SRAM cells have greatly reduced power consumption as well as leakage current, the identical technique is utilized. The performance of FINFETbased SRAM cells has been evaluated to that of conventional, advanced MOSFET-based Static RAM cells.
Key Words: Cadence, SRAM, CMOS, 7T SRAM Cell, Leakage Power.
1. INTRODUCTION Several industries benefit greatly from artificial intelligence as well as machine learning [1]. Such techniques involve extensive data processing as well as calculation. Modifications to the hardware execution of AI technologies are essential for energy-efficient applications like the IoT [2]. One of the most promising approaches to enhancing energy efficiency is the use of in-memory computing. Multiple forms of in-memory multiplication, as well as logical operations, are already a reality. Khwa et al. [3] to perform ternary multiplication, a six transistor (6T) cell was employed in conjunction with a reference voltage generating column; Yin
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M.Srinivas et.al [12] Power loss during standby is mostly due to leakage currents, and they are unfortunately on the rise. Sub-threshold leakage increases as the threshold voltage is lowered because the gate current leaks more quickly. As the number of people who rely on mobile devices increases, so does concern over leakage energy use. If you rarely use your phone and instead leave it in standby, you can improve
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