International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 10 Issue: 06 | Jun 2023
p-ISSN: 2395-0072
www.irjet.net
A Comparative Performance Analysis of Copper on Chip and CNTFET Nano Interconnects Arun Kundu1, Manoj Kumar2
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quickly, which has led to the miniaturisation of semiconductor industries. Power consumption in the Deep Sub Micron domain has become a significant problem due to leakage current, hence researchers are always looking at different strategies to reduce it. There are other approaches available for the same thing, and using carbon nanotube technology is one of the methods that shows promise for effectively designing low power circuits. In this article, new methods for reducing leakage power are introduced. In this work, the primary performance metrics of the CNTFET and the Copper on Chip Nano-interconnect have been compared. By combining process variation in CU and CNT Interconnects with tube variation at 32nm technology, we were able to quantify the effects of ION and IOFF current. We also examined how the performance of digital circuits changed as technology advanced. The various simulation results show that applying 10% deviation from the mean to various device characteristics parameters, including source and drain doping concentration with Cu and CNTFET interconnects for NFET and PFET with a range of tubes from 1 to 16, is effective. These parameters include length of gate (L-Tube), width (WTube), threshold voltage (Vth), thickness (total), and source&drain doping concentration. All of the experimental results were obtained using the HSPICE simulator and the 32nm Berkley Predictive Technology module with the CU and CNT SPICE models at 27 °C temperature.
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Research Scholar, ECE Department1, Om Sterling Global University, Hisar, Haryana (India)2 Associate professor, ECE Department, Om Sterling Global University, Hisar, Haryana (India)2 -----------------------------------------------------------------------***-------------------------------------------------------------------------Abstract – The digital electronics industry has advanced
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Di Undoped CNT SUBSTRA
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Figure 1: 3D Structure of CNTFET
2. CNTFET CNTs are Hexagonal package of atoms known as benzene ring. This ring makes a Graphene sheet. Further, this rolledup sheet constitutes CNTs. The roll with diameter of less than 1nm is classified as SWCNT. When such tubes placed in bundles, the bundles are known as MWCNT. The superlative monotonous electric as well as architectural features of CNTFET suggest as definite choice for Interconnect material for long terms. The CNTs functioning c a n b e stated as in figure 2.
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1. INTRODUCTION Carbon Nanotubes possess invaluable electric as well as monotonous features. CNTs are an Interconnect material in VLSI technology. CNTs major classifications are singlewalled (SWCNT) and multi-walled (MWCNT). Single-walled CNTs based devices have dimensions less than 1nm where as Multi-walled CNTs have device dimensions < 100nm [13]. Figure 1 represents three dimensional architecture of CNTFET.
Carbon Nano Tube
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Key Words – ION and IOFF, CNTFET, Mean, Standard Deviation, Power Consumption.
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Figure 2: Top View of CNTFET The CNTFET architecture is much similar to conventional MOSFET structure barring source-drain channel region being interchanged by CNTs. At the same time, sourcedrain channel is doped heavily, resulting in elevated
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