International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 10 Issue: 06 | Jun 2023
p-ISSN: 2395-0072
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Design and Performance Evaluation of a 64-bit SRAM Memory Array Utilizing Modern Deep Submicron Technology Sonali Verma 1, Dileep Kumar 2 1 Department of Electronics & Communication Engineering, Goel Institute of Technology and Management,
Faizabad Road near Indira Canal Lucknow 2 Department of Electronics & Communication Engineering, Goel Institute of Technology and Management,
Faizabad Road near Indira Canal Lucknow ---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract - Electronic digital computers make use of
high-energy charged particles. Electron-hole pairs are produced whenever a particle collides with a digital logic circuit. The electric field separates these electron-hole pairs, which are then collected at sensitive node. A short voltage pulse is created as a result of charge accumulation. [5]. High-density memory, as well as electronic devices, are critical in biological applications. The main rationale for operating memory at low voltage is to maximize battery life while using less energy as possible. The read process noise immunity of a normal 6T SRAM cell is modest. The noise immunity decreases significantly as supply voltage lowers. As a result, standard 6T SRAM is unable to operate at low supply voltages. The utilization of decoupled 7T and 8T SRAM cells is known to enhance noise immunity during read operations by isolating storage nodes from the bit lines. However, it is worth noting that these cells exhibit considerable leakage power. Even if millions of SRAM cells may be kept in a "standby" state, the memory's power consumption has risen exponentially. [6][7][8][9][10]. Embedded memory configuration has been enhanced by modern VLSI (very-large-scale integration) systems. Differentiating between DRAM (dynamic random-access memory) & SRAM (static random-access memory) is crucial when dealing with ram. The word "static" refers to a circuit in which all components are either coupled to Vdd or VSS at all times, eliminating the floating node problem and allowing DRAM cells to be constructed using just capacitors and a single transistor. The word "random" means the data may be accessed whenever needed and from wherever it may be stored. Memory searching and bit storing are required for access. Every cell store one bit. [11][12][13]. SRAM cells are built from transistors & latches. Capacitors were employed for both storing data and retrieving it, but the process of charging and discharging them required a lot of energy and time. This benefit is a major reason why SRAM cells are widely employed in SoCs. [14][15][16][17], where they are an essential component of design and implementation. In response to rising need for decreased power consumption and higher productivity in current SoC technologies, a multiplicity of SRAM cell designs has been created, each of which is optimized for excellent performance. This has resulted in a significant increase in the amount of memory that can be stored in a given amount of space. 7T SRAM
memory, that is used to both temporarily and permanently stores data and instructions. Random Access Memory (RAM) is antithesis of serial access memory since it allows simultaneous reading and writing. The quantity of complexity that can be generated on a single chip has been significantly increased due to technological advancements. Every electronic part is now expected to have a small form factor, low power consumption, cheap price, and high performance. As a consequence of these variables, designers have been compelled to concentrate on the sub-micron scale, which is where leakage qualities play an essential part. Memory is essential because several electrical components, particularly digital ones, are designed to store information. This highlights the importance of memory. Leakage current is most significant factor in SRAM power consumption. The 1-bit 7T SRAM cell was used in this article to build a 64-bit SRAM memory array utilizing CMOS technology and a 0.7volt supply. This SRAM was created using an 8-bit by 8-bit and 1-bit by 1-bit arrangement. The substrate voltage of 7T SRAM may be lowered using the adaptive body bias approach without losing functionality. We investigate the utilization of Adaptive body biassing to learn to manage substrate voltages of a transistor and show that it is most effective in sub threshold circuits, where it can eliminate exhibit deviation with Low power. In terms of read and write power consumption, suggested 64-bit memory array SRAM outperformed current 8T and 7T SRAM. Key Words: SRAM, Leakage Power, 7T SRAM Cell, CMOS, Cadence.
1. INTRODUCTION Satellite communication programs have found widespread usage in modern era. They have several applications, including catastrophe monitoring, communication, and military activities. To minimize maintenance and production costs, lighter satellites are manufactured as technology advances. [1][2][3][4]. The small size of lightweight satellites necessitates a high memory cell density. SRAM cells are suitable for satellite digital data processing and control systems because of their high packing density and better logic performance. Space has
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