International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 10 Issue: 06 | Jun 2023
p-ISSN: 2395-0072
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FPGA Implementation of Accelerated Finite Impulse Response Filter for EEG Analysis Nithish Vaasu, Mohammed Ashfaque A, G Bhuvanesh, Sanjith S, Sainath S Student, Dept. of Electronics and Communication Engineering PSG College of Technology Coimbatore, India Student, Dept. of Electronics and Communication Engineering PSG College of Technology Coimbatore, India Student, Dept. of Electronics and Communication Engineering PSG College of Technology Coimbatore, India Student, Dept. of Electronics and Communication Engineering PSG College of Technology Coimbatore, India Assistant Professor, Dept. of Electronics and Communication Engineering PSG College of Technology Coimbatore, India ----------------------------------------------------------------------***--------------------------------------------------------------------Abstract — Majority of the real time signal processing environments involve the processing of ample amount of data at a time. EEG Signal Processing is one such example, which demands the processing of EEG signals recorded over a larger time period for the study of brain activity. An electroencephalogram (EEG) is a test that measures electrical activity in the brain using small, metal discs (electrodes) attached to the scalp. The work presented in this paper is inclined towards the implementation of hardware accelerated Finite Impulse Response (FIR) filter for the processing of EEG signals. Discrete Wavelet Transform is used in the time-frequency analysis of EEG signals. The design is exported as an FPGA overlay which accelerates the processing of the EEG signal. We have used PYNQ –Z2 FPGA development board to implement the hardware accelerator.
(15–30 Hz), and gamma (30–60 Hz). These individual frequency sub-bands may better represent brain dynamics than the EEG signal itself. Indeed, they contain more precise information on the neuronal activities and raise some alterations that do not appear in the raw EEG [1]. Hardware acceleration combines the flexibility of general-purpose processors, such as CPUs, with the efficiency of fully customized hardware (FPGA boards), such as GPUs and ASICs, increasing efficiency by orders of magnitude when any application is implemented in the digital computing systems FPGAs are reconfigurable hardware chips that can be reprogrammed to implement varied combinational and sequential logic. Their programmability imparts excellent flexibility and the opportunity to quickly develop a prototype of a circuit keeping the same hardware this is due to the parallelism of FPGA accelerators which offer data, task, and pipeline parallelism, resulting in faster data process execution. A FPGA also complies with the high performance and low power operational needs of a given application, resulting in a high-performance ratio.
Keywords—Electroencephalography, EEG-SignalProcessing, PYNQ-Z2, Accelerated FIR Filter, Signal Processing.
I. INTRODUCTION Signal processing, is a major engineering domain which is used to manipulate, analyses or synthesize various types of signals to extract out useful information. It is mostly done in a computer mainframe which has a generic DSP processor. The establishment of ASICs and FPGA prototyping aids in the development of dedicated hardware for a specific purpose. We have considered EEG signal processing in this paper and the implementation of the same in an FPGA development board, with an observation in the acceleration of processing speed by a factor of two (approx.)
II.
RELATED WORKS
Analyzing EEG data is an exceptional way to study cognitive processes. It can help doctors establish a medical diagnosis, researchers understand the brain processes that underlie human behavior, and individuals to improve their productivity and wellness.
Pari Jahankhaani et al. [2] proposed the DB4 algorithm or wavelet feature extraction method to classify the EEG signal into different small signals based on their frequencies for decision making. Hojjat Adeli et al. [3] investigated on discrete Daubechies and harmonic wavelets for analysis of epileptic EEG records. It is used to analyze and characterize epileptiform discharges. M. Popovic, M. Jankovic [4] proposed techniques to accelerate the actual program for optimum linear-phase FIR filter design. The time required for the design of these filters can be cut down by up to 2.5 times by utilizing these strategies independently. The execution time can be increased by up to 6 times when new methods are combined with other well-known approaches.
There are commonly five sub-bands on the EEG signal: delta (0–4 Hz), theta (4–8 Hz), alpha (8–15 Hz), beta
V.S. Lin et al. [5] has implemented FIR filter using dedicated hardware mapped onto a Xilinx FPGA board. For
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