International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 10 Issue: 05 | May 2023
p-ISSN: 2395-0072
www.irjet.net
SRAM BASED IN-MEMORY MATRIX VECTOR MULTIPLIER K.G.Venkata krishna 1, P. Hema naga sai surya kumar 2, S. Meghana 3, A. Reddy prasad reddy 4, G. Muni jayanth 5 1 Assistant Professor, Department of Electronics and Communication Engineering, Krishna University College of
Engineering and Technology Krishna University, Machilipatnam Andhra Pradesh, India. .
2 U.G Student, Department of Electronics and Communication Engineering, Krishna University, Machilipatnam,
Andhra Pradesh, India.
3 U.G Student of Department of Electronics and Communication Engineering, Krishna University, Machilipatnam
Andhra Pradesh, India.
4 U.G Student of Department of Electronics and Communication Engineering, Krishna University, Machilipatnam
Andhra Pradesh, India.
5 U.G Student of Department of Electronics and Communication Engineering, Krishna University, Machilipatnam
Andhra Pradesh, India. ---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract - The weights stored in the SRAM are turned into
dynamical state of charging resistance-based memory devices to conduct certain computations directly in the memory. An IMC-based system may be used to accomplish a variety of computing tasks, including logical operations, arithmetic operations, and even certain machine learning activities.
proportional voltages using a D/A converter, which is how the SRAM-based matrix-vector multiplier for in-memory computation functions. These voltages are subsequently multiplied by a switched-capacitor stage using an m-bit digital input activation. Finally, charge sharing is used to gather the output voltages associated with the various multiplication outcomes along one column.
1.1 Motivation The need for low-power integrated circuits has greatly increased over the past several years as a result of the increasing expansion of battery-operated devices including wireless communication units, portable entertainment devices, and implementable bio-medical chips. SRAM will eventually account for more than 60% of SoCs, predicts the International Technology Roadmap for Semiconductors (ITRS). The problem of consuming power and space is significantly solved when the technology scales by greatly increasing the transistor density in the SRAM units.
The needed circuit size, calculation time, and power consumption grow linearly with the specified architecture. For the energy usage in switches and capacitors, analytical formulae are provided. Additionally, the effect of manufacturing mismatch on the precision of analogue computing is looked at. Key Words: Analog Computation, Hardware Accelerator, In-Memory Computation, SRAM, DRAM
1.INTRODUCTION
1.2 Objective
During computations, a lot of data is sent back and forth between the physically distinct memory and processor units of standard Von-Neumann computing systems. It is necessary to reevaluate both the well-established chargebased memory technologies, such as SRAM, DRAM, and Flash, as well as the emerging resistance-based nonvolatile memory technologies in order to get around the limitations of the traditional Von-Neumann-based architectures, which enforce an assertive separation of the processing unit and the memory subsystem.
The in-memory matrix-vector multiplier built on SRAM has as its primary goal a reduction in the amount of time required to complete computations. Performance may be improved and power consumption can be decreased by utilising SRAM technology.
2. LITERATURE SURVEY 2.1 Static Random Access Memory.
It is becoming more and more obvious that switching to computing architectures with co-located logic and memory is necessary for application domains like artificial intelligence (AI). IMC, a unique non-Von Neumann computing paradigm, uses the physical characteristics and
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In SoCs, embedded SRAMs may take up the bulk of the chip space. Modern scaled-down technologies' increasing process spreads and non-catastrophic defect-related vulnerability to external factors might jeopardise SRAM cells' stability, which is measured by their low Static Noise Margin (SNM). In a cell
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