Performance analysis of NOR CAM cell using CMOS-HP, CMOS-LP and FinFET 16nm technology

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Performance analysis of NOR CAM cell using CMOS-HP, CMOS-LP and FinFET 16nm technology

Abstract - Content addressable memory (CAM) is used in many applications such as Network routers, Cache controllers and low power CPU design. It searches total memory array in one clock cycle. CAM cell contains memory cell and match circuit. Memory cell contains stored data and match circuit compares the input data and stored data. Search operation happens in parallel fashion, access time is less and power dissipation will be more. This paper presents functionality of NOR based CAM cell implemented using CMOS-LP, CMOS-HP, FinFET 16nm technology and power reduction in HSPICE tool.

Key Words: NOR CAM; FinFET; CMOS-LP; CMOS-HP; HSPICEtool

1.INTRODUCTION

In present day scenario there is a need of better performancewithrespecttoincreaseinspeedwithreduced powerdissipation.Thehigh frequencyofCAMisachieved throughscalingthetransistors.Scalingoftransistorsleadsto reductioninchannellength.Thiswillreducethetransittime of the charge carriers which increases the frequency of operation of the device [1]. In order to overcome short channeleffectsFinFETshasevolved.FinFETshasbecomean alternativebecauseofitsscalabilityandcompatibilitywith planarCMOS[2].

Content addressable memory (CAM) is associative memorywheredataisgivenasinputandaddressisgivenas output. The search operation in CAM happens in parallel fashionand henceCAMisfaster whichcauseshighpower dissipationandlessaccesstime[3]. IntheFig1,thedatais senttothesearchdataregisterthroughsearchlinestothe memorycells.Thisinputdataiscomparedwiththestored data.Whenthestoreddataismatchedwiththeinputdata, thecorrespondingmatchlinewillbeenabled.Theaddressof thematcheddatawillbeconsideredastheoutput.

1.1 CMOS

BothNMOSandPMOShassimilarcharacteristicsduring onandoffstateandhenceitisusedinCMOSTechnologyto realizevariouslogicfunctions.OverBipolarortheprevious popularNMOStechnologiesCMOStechnologyhasextremely low power consumption in static conditions as they draw power only during switching operation. This allows integratingmuchlargernumberoflogicgatesontheVLSIIC whencomparedtoBipolarorNMOStechnologies.

InordertoimplementCMOS-HPtheVDDandVthiskept lower in order to improve the speed in performance. Likewise,inordertoimplementtheCMOS-LPtheVDDand Vthwillbehighinordertoreducethepowerdissipationin transistor

1.2 FINFET

FinFETisathree-dimensionaltransistorwhichismade onSiliconwafers(BulkFinFET)orsilicononinsulator(SoI FinFET). It is made of a thin fin material embedded on a substrate.Channelwillbefullywrappedaroundbythegate ofdevice,whichhavecontroloverchannelasshowninFig2 [4].

ContinuousscalingofMOSFETtolowertechnologynodes hasbecome verychallengingaspect. Due to short channel effects and leakage current issues made a way to the evolutionofFinFETtechnology.

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 10 Issue: 04 | Apr 2023 www.irjet.net p-ISSN: 2395-0072 © 2023, IRJET | Impact Factor value: 8.226 | ISO 9001:2008 Certified Journal | Page1231
Ratnamala S1 , Dr. 1Dept. of ECE BMS College of Engineering, Bengaluru, India 2Proffessor, Dept. of ECE BMS College of Engineering, Bengaluru, India
***
Figure1.CAMconceptualdiagram

Most widely used operating modes of FinFET are explained below. FinFET structure consists of two gates namely,frontend(G1)andbackend(G2)asshowninFig3.

When there is a match in D and SL disables the pulldown pathandMLremainsinVDD[5].

Theareaconsumptionismoreandthefrontgateandthe backgateareoperatedindividually.

Theswitchingspeedismoreandithasgoodresistance whencomparedtoothermodes,asboththefrontandback gatesareshorted.

Inthereversebiasmode,inordertosuppresstheeffects ofsubthresholdleakagecurrentthebackgateofFinFETis associatedtoareversebiasvoltage.

A CAM is a special type of memory device which implementsalook-uptablefunction.ACAMisclassifiedinto twotypes,binaryCAMandternaryCAM.

Binary CAM will cache only ‘0’ and ‘1’. It is used in applications which need exact match between the stored data and input data. Table1 represents truth table of the BCAM

ACAMcellhastwobasicfunctionalities:storingabitin SRAMandcomparisonofabit.NOR-typeCAMcellisshown inFig5.Thecomparisonbetween andDwhicharestored inmemory,andthesearchdataissentonthesearchline andSL.ByusingdynamicXNORlogiccomparisoncircuitthe outputisdrawnfrommatchlineML.ThemismatchofDand SL activates the pulldown path, connects ML to ground.

Ternary CAM stores three states ‘0’, ‘1’ and ‘X’. The ‘X’ state is additional state referred to as the “mask bit” or “don’tcarebit”.TCAMisusedforapplicationsforbothexact andpartialmatches.Table4representstruthtableforTCAM [6].

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 10 Issue: 04 | Apr 2023 www.irjet.net p-ISSN: 2395-0072 © 2023, IRJET | Impact Factor value: 8.226 | ISO 9001:2008 Certified Journal | Page1232
Fig2.StructureofFinFET Fig3.CrosssectionviewofFinFET A. Independent gate mode B. Shorted gate mode C. Reverse bias mode 2. METHODOLOGY Fig4.10-TNORtypeCAMcell 3. CIRCUIT IMPLEMENTATION A. Binary CAM (BCAM)
Storedata Searchdata Outcome 0 0 1 0 1 0 1 0 0 1 1 1
Table1.TruthtableofBCAM B. Ternary CAM (TCAM)
Storedata Searchdata Outcome 0 0 1 0 1 0 0 X 1 1 0 0 1 1 1 1 X 1
Table4.TCAMtruthtable

4. WORKING

Fig 5. shows SRAM based BCAM cell using XNOR transistorlogiccircuit.Thedataisstoredandreadsimilarto SRAMatnodeVxwhilesearcheddataissenttolinesSLand SLB. When there is a mismatch between stored data and searcheddata,matchlinevoltageisdischargedtoGNDand mismatchedoutcomeispresented.

Fig 6. shows SRAM based TCAM with XNOR transistor logic circuit as a compare circuit, where data is stored in nodeVxatSRAM1andVyatSRAM2.

Fig 7. shows SRAM based BCAM cell using XNOR transmissiongatelogiccircuit.TheCAMoperationhappens thesameasdiscussedinprevioussections.InBCAMXNOR transistorlogic,thetransistorcountismoreaswecanseein Fig 5. Thus, transistor XNOR logic circuit is replaced with transmissionXNORlogiccircuitinmatchcircuit.Fig8.shows SRAM based TCAM with XNOR transmission gate logic circuit.

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 10 Issue: 04 | Apr 2023 www.irjet.net p-ISSN: 2395-0072 © 2023, IRJET | Impact Factor value: 8.226 | ISO 9001:2008 Certified Journal | Page1233 X 0 1 X 1 1 X X 1
4.1. CAM cell with XNOR transistor logic Fig5.BCAMwithXNORtransistorlogic Fig6.TCAMwithXNORtransistorlogic
Vx Vy SL1c SL1 PUP PUD ML 1 0 1 0 ON OFF 1 1 0 0 1 OFF ON 0 0 1 1 0 OFF ON 0 0 1 0 1 ON OFF 1
Table2TruthtableforBCAMXNORwithTransistorcircuit 4.2. CAM cell with XNOR logic using transmission gate

Fig9.showsSRAMbased BCAMcellusingXNORswitch stacklogiccircuit.TheoperationoftheCAMcellisdiscussed in the above section. In previous section 1.b. the power dissipation is more. Hence in this section the proposed circuitreducesthepowerdissipation.Theworkingofthis circuitisunderstoodwiththehelpofthetruthtable.Fig10. showsSRAMbasedTCAMwithXNORtransistorlogiccircuit.

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 10 Issue: 04 | Apr 2023 www.irjet.net p-ISSN: 2395-0072 © 2023, IRJET | Impact Factor value: 8.226 | ISO 9001:2008 Certified Journal | Page1234
2
Vx Vy SL1 SL1c Pass1 Pass2 ML 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 1 1 0 1 0 0 0 1 0 1 1 0 1
Figure7.BCAM withXNORTransmissiongatelogic Table TruthtableforCAMXNORwithTransmissiongate Fig8.TCAMwithXNORtransmissiongate 4.3. CAM cell with XNOR logic using novel comparison circuit Figure9. BCAMwithXNORswitchstacklogic Fig10.TCAMwithXNORswitchstack

5. RESULTS AND SIMULATION

AlltheCAMoperationsisperformedin16nmtechnology byusingCMOS-LP,CMOS-HPandFinFET.Poweranddelay valuesarecomparedforeachofthecircuitdescribedabove

Bycomparingtheobtainedvalues,wecanseethatthere is 15% - 19% reduction in power dissipation in FinFET BCAMwhencomparedothercircuits.19% -25%ifpower dissipationinreducedinFinFETTCAMwhencomparedwith othercircuits.

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 10 Issue: 04 | Apr 2023 www.irjet.net p-ISSN: 2395-0072 © 2023, IRJET | Impact Factor value: 8.226 | ISO 9001:2008 Certified Journal | Page1235
Vx Vy Sl1 Sl1c Pass P4 P5 N7 N8 ML 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1
Table3.TruthtableforBCAMXNORwithswitchstack logic Figure11.PowermeasurementsofCMOS-HPBCAM Figure12.PowermeasurementsofCMOS-LPBCAM Figure13.PowermeasurementsofFinFETBCAM Figure14.PowermeasurementsofCMOS-HPTCAM Figure15.PowermeasurementsofCMOS-LPTCAM Figure16.PowermeasurementsofFinFETTCAM
CMOS-LP CMOS-HP FinFET BCAM 4.7281E-06 1.4406E-04 1.1597E-06 TCAM 1.0749E-03 4.7961E-05 4.0095E-05
Table4. AveragepowerofCAM(W)

From the obtained delay values, there is 20% - 24% reductionofdelayinFinFETBCAMwhencomparedother circuits.Around27%-37%ofreductionindelayisseenin FinFETTCAMwhencomparedtoothercircuits.

6. CONCLUSIONS

ThisprojectexplainsthedesignandworkingofCAMwhich consists SRAM as memory cell and XNOR as comparison circuit.Byadoptingdifferenttechnologies,theperformance of BCAM and TCAM are investigated. The CAM operations are carried out by using CMOS-LP, CMOS-HP and FinFET technology and obtained power and delay values are compared for different compare circuit. From the experiment, FinFET CAM cells with XNOR switch stack circuitgivesbetterperformancewithlesspowerdissipation anddelaywhencomparedtootherlogiccircuitsinall the technologynodes

International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 10 Issue: 04 | Apr 2023 www.irjet.net p-ISSN: 2395-0072 © 2023, IRJET | Impact Factor value: 8.226 | ISO 9001:2008 Certified Journal | Page1236
Figure19.DelaymeasurementsofCMOS-HPBCAM Figure17.DelaymeasurementsofCMOS-LPBCAM Figure18.DelaymeasurementsofFinFETBCAM Figure19.DelaymeasurementsofCMOS-HPTCAM Figure20.DelaymeasurementsofCMOS-LPTCAM Figure21.DelaymeasurementsofFinFETTCAM
CMOS-LP CMOS-HP FinFET BCAM 4.8487E-08 3.5348E-08 3.0531E-08 TCAM 4.0112E-08 3.1738E-08 3.0201E-08
Table7.AveragedelayofCAM(s)

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